Add Support for Luckfox Pico Zero (#310)

* sysdrv/source/kernel/arch/arm/boot/dts : Add Luckfox Pico Zero device tree files

Signed-off-by: eng29 <eng29@luckfox.com>

* project/cfg/BoardConfig_IPC : Add Luckfox Pico Zero BoardConfig file

Signed-off-by: eng29 <eng29@luckfox.com>

* project/build.sh : Add the lunch menu item of Luckfox Pico Zero

Signed-off-by: eng29 <eng29@luckfox.com>

* project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-config/usr/bin/luckfox-config : Add support for Luckfox Pico Zero

Signed-off-by: eng29 <eng29@luckfox.com>

* sysdrv/drv_ko/wifi/insmod_wifi.sh : Use the device ID as the basis for loading the AIC8800DC driver

Signed-off-by: eng29 <eng29@luckfox.com>

* sysdrv/source/kernel/drivers/media/i2c : Add the ISG1321 sensor driver

Signed-off-by: eng29 <eng29@luckfox.com>

* sysdrv/source/kernel/drivers/media/i2c/imx415.c : Add 4-lane 15fps mode for Luckfox Pico Zero

Signed-off-by: eng29 <eng29@luckfox.com>

* sysdrv/source/kernel/drivers/media/platform/rockchip/isp/hw.c : Add the "rockchip,unite" parameters

Signed-off-by: eng29 <eng29@luckfox.com>

* sysdrv/source/kernel/arch/arm/configs/luckfox_rv1106_linux_defconfig : Add IMX415 and ISG1321 support

Signed-off-by: eng29 <eng29@luckfox.com>

* project/app/rkipc/rkipc/common/network/network.c : Cancel the status monitoring for wlan0 and usb0

Signed-off-by: eng29 <eng29@luckfox.com>

* project/app/rkipc/rkipc/src/rv1106_ipc : Add IMX415 and ISG1321 support for Luckfox Pico Zero

Signed-off-by: eng29 <eng29@luckfox.com>

* media/isp/release_camera_engine_rkaiq_rv1106_arm-rockchip830-linux-uclibcgnueabihf/isp_iqfiles : Add ISG1321 iqfile

Signed-off-by: eng29 <eng29@luckfox.com>

* sysdrv/drv_ko/insmod_ko.sh : Register ISG1321 driver during boot process

Signed-off-by: eng29 <eng29@luckfox.com>

* sysdrv/tools/board/buildroot/luckfox_pico_defconfig : Add rsync command for backup

Signed-off-by: eng29 <eng29@luckfox.com>

---------

Signed-off-by: eng29 <eng29@luckfox.com>
This commit is contained in:
luckfox-eng29
2025-08-14 14:38:50 +08:00
committed by GitHub
parent e2b0ffa22e
commit 9942437537
20 changed files with 5960 additions and 43 deletions

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@@ -0,0 +1,445 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-evb.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/display/media-bus-format.h>
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk0p7 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0";
};
reserved_memory: reserved-memory {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
ranges;
mmc_ecsd: mmc@3f000 {
reg = <0x3f000 0x00001000>;
};
};
acodec_sound: acodec-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rv1106-acodec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
simple-audio-card,codec {
sound-dai = <&acodec>;
};
};
dsm_sound: dsm-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,dsm-sound";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&dsm>;
};
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_arm: vdd-arm {
compatible = "regulator-fixed";
regulator-name = "vdd_arm";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-init-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
leds: leds {
compatible = "gpio-leds";
work_led: work{
gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "activity";
default-state = "on";
};
};
out_osc_mia1321: out-osc-mia1321 {
compatible = "fixed-clock";
clock-output-names = "out-osc-mia1321";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
out_osc_imx415: out-osc-imx415 {
compatible = "fixed-clock";
clock-output-names = "out-osc-imx415";
clock-frequency = <37125000>;
#clock-cells = <0>;
};
cam_ircut0: cam_ircut {
status = "okay";
compatible = "rockchip,ircut";
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
};
/***************************** audio ********************************/
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&acodec {
#sound-dai-cells = <0>;
status = "okay";
};
/************************* FIQ_DUBUGGER ****************************/
&fiq_debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";
};
/***************************** USB *********************************/
&u2phy {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usbdrd {
status = "okay";
};
&usbdrd_dwc3 {
extcon = <&u2phy>;
status = "okay";
};
/***************************** DSM *********************************/
&dsm {
status = "disabled";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
/*************************** CSI *********************************/
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
//mia1321
csi_dphy_input0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mia1321_out>;
data-lanes = <1 2>;
};
//imx415
csi_dphy_input1: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx415_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&i2c4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c4m2_xfer>;
mia1321: mia1321@60 {
compatible = "imagedesign,mia1321";
reg = <0x60>;
clocks = <&out_osc_mia1321>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_io_1>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "MIA1321";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
mia1321_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2 3 4>;
};
};
};
imx415: imx415@37 {
compatible = "sony,imx415";
status = "okay";
reg = <0x37>;
clocks = <&out_osc_imx415>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cam_io_1>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-36IRC-8M-F20";
lens-focus = <&cam_ircut0>;
port {
imx415_out: endpoint {
remote-endpoint = <&csi_dphy_input1>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
/***************************** ADC ********************************/
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&tsadc {
status = "okay";
};
/**************************** PINCTRL ******************************/
// SPI
&spi0 {
pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
// I2C
&i2c1 {
pinctrl-0 = <&i2c1m1_xfer>;
};
&i2c2 {
pinctrl-0 = <&i2c2m0_xfer>;
};
&i2c3 {
pinctrl-0 = <&i2c3m0_xfer &i2c3m1_xfer &i2c3m2_xfer>;
};
&i2c4 {
pinctrl-names = "default", "config";
pinctrl-0 = <&i2c4m2_xfer>;
pinctrl-1 = <&i2c4m0_xfer &i2c4m1_xfer>;
};
// UART
&uart0 {
pinctrl-0 = <&uart0m0_xfer &uart0m1_xfer>;
};
&uart1 {
pinctrl-0 = <&uart1m1_xfer>;
};
&uart3 {
pinctrl-0 = <&uart3m0_xfer &uart3m1_xfer>;
};
&uart4 {
pinctrl-0 = <&uart4m0_xfer &uart4m1_xfer>;
};
&uart5 {
pinctrl-0 = <&uart5m1_xfer>;
};
// PWM
&pwm0 {
pinctrl-0 = <&pwm0m1_pins>;
};
&pwm1 {
pinctrl-0 = <&pwm1m0_pins &pwm1m1_pins &pwm1m2_pins>;
};
&pwm2 {
pinctrl-0 = <&pwm2m0_pins &pwm2m1_pins &pwm2m2_pins>;
};
&pwm3 {
pinctrl-0 = <&pwm3m1_pins &pwm3m2_pins>;
};
&pwm4 {
pinctrl-0 = <&pwm4m0_pins &pwm4m1_pins &pwm4m2_pins>;
};
&pwm5 {
pinctrl-0 = <&pwm5m1_pins &pwm5m2_pins>;
};
&pwm6 {
pinctrl-0 = <&pwm6m1_pins &pwm6m2_pins>;
};
&pwm7 {
pinctrl-0 = <&pwm7m0_pins &pwm7m1_pins>;
};
&pwm8 {
pinctrl-0 = <&pwm8m1_pins>;
};
&pwm9 {
pinctrl-0 = <&pwm9m1_pins>;
};
&pwm10 {
pinctrl-0 = <&pwm10m1_pins &pwm10m2_pins>;
};
&pwm11 {
pinctrl-0 = <&pwm11m1_pins &pwm11m2_pins>;
};
&pinctrl {
cam {
cam_io_0: cam-io-0 {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
cam_io_1: cam-io-1 {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
spi0 {
spi0m0_clk: spi0m0-clk {
rockchip,pins = <1 RK_PC1 4 &pcfg_pull_none>;
};
spi0m0_mosi: spi0m0-mosi {
rockchip,pins = <1 RK_PC2 6 &pcfg_pull_none>;
};
spi0m0_miso: spi0m0-miso {
rockchip,pins = <1 RK_PC3 6 &pcfg_pull_none>;
};
spi0m0_cs0: spi0m0-cs0 {
rockchip,pins = <1 RK_PC0 4 &pcfg_pull_none>;
};
};
};

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@@ -0,0 +1,161 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-luckfox-pico-zero-ipc.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/display/media-bus-format.h>
/ {
model = "Luckfox Pico Zero";
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1106g3";
restart-poweroff {
compatible = "restart-poweroff";
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
uart_rts_gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart1m0_rtsn>;
pinctrl-1 = <&uart1_gpios>;
BT,wake_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
/**********CRU**********/
&cru {
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ARMCLK>,
<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
<&cru HCLK_PMU_ROOT>, <&cru CLK_500M_SRC>;
assigned-clock-rates =
<1188000000>, <700000000>,
<1104000000>,
<400000000>, <200000000>,
<100000000>, <300000000>,
<100000000>, <100000000>,
<200000000>, <700000000>;
};
/**********NPU**********/
&npu {
assigned-clock-rates = <700000000>;
};
/**********EMMC**********/
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
non-removable;
// mmc-hs200-1_8v;
rockchip,default-sample-phase = <90>;
no-sdio;
no-sd;
memory-region-ecsd = <&mmc_ecsd>;
post-power-on-delay-ms = <0>;
status = "okay";
};
&fiq_debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";
};
/**********SDIO-WIFI**********/
&sdmmc {
max-frequency = <50000000>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
//non-removable;
rockchip,default-sample-phase = <90>;
// no-sd;
// no-mmc;
supports-sdio;
mmc-pwrseq = <&sdio_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
status = "okay";
};
&pinctrl{
sdmmc0{
sdmmc0_det: sdmmc0-det {
rockchip,pins =
/* sdmmc0_det */
<3 RK_PA1 1 &pcfg_pull_up>;
};
};
};
/**********SD_CARD**********/
&sdio {
max-frequency = <50000000>;
no-sdio;
no-mmc;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
/**********ETH**********/
&gmac {
status = "disabled";
};
/**********USB**********/
&usbdrd_dwc3 {
status = "okay";
dr_mode = "peripheral";
//dr_mode = "host";
};
/**********RTC**********/
&rtc {
status = "okay";
};
/**********BT**********/
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
};
&pinctrl {
wireless-bluetooth {
uart1_gpios: uart1-gpios {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
/**********SPI**********/
&spi0 {
status = "disabled";
spidev@0 {
spi-max-frequency = <50000000>;
};
};

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@@ -196,7 +196,9 @@ CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ROCKCHIP_CIF=m
CONFIG_VIDEO_ROCKCHIP_ISP=m
CONFIG_VIDEO_RK_IRCUT=y
CONFIG_VIDEO_IMX415=m
CONFIG_VIDEO_MIS5001=m
CONFIG_VIDEO_MIA1321=m
CONFIG_VIDEO_SC3336=m
CONFIG_DRM=y
CONFIG_DRM_EDID=y