diff --git a/media/isp/release_camera_engine_rkaiq_rv1106_arm-rockchip830-linux-uclibcgnueabihf/isp_iqfiles/mia1321_MIA1321_30IRC-F16.json b/media/isp/release_camera_engine_rkaiq_rv1106_arm-rockchip830-linux-uclibcgnueabihf/isp_iqfiles/mia1321_MIA1321_30IRC-F16.json new file mode 100755 index 000000000..c7434933d --- /dev/null +++ b/media/isp/release_camera_engine_rkaiq_rv1106_arm-rockchip830-linux-uclibcgnueabihf/isp_iqfiles/mia1321_MIA1321_30IRC-F16.json @@ -0,0 +1,2563 @@ +{ + "sensor_calib": { + "resolution": { + "width": 2688, + "height": 1520 + }, + "Gain2Reg": { + "GainMode": "EXPGAIN_MODE_NONLINEAR_DB", + "GainRange": [1, 246.45, 16, 0, 1, 16, 3943], + "GainRange_len": 7 + }, + "Time2Reg": { + "fCoeff": [0, 0, 1, 0.5] + }, + "CISGainSet": { + "CISAgainRange": { + "Min": 1, + "Max": 29.5 + }, + "CISExtraAgainRange": { + "Min": 2.6, + "Max": 76.7 + }, + "CISDgainRange": { + "Min": 1, + "Max": 125 + }, + "CISIspDgainRange": { + "Min": 1, + "Max": 1 + }, + "CISHdrGainIndSetEn": 1 + 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0 + }], + "measiso_len": 1 + }], + "zoom_meas_len": 1, + "meascfg_tbl": [{ + "tbl_idx": 0, + "from_awb": 0, + "from_ynr": 0, + "afmThres": 4, + "gammaY": [0, 45, 108, 179, 245, 344, 409, 459, 500, 567, 622, 676, 759, 833, 896, 962, 1023], + "gaus_coe": [0, 64, 0, 0, 64, 0, 0, 0, 0], + "dnscl_mode": "CalibDbV2_AF_DNSCL_1", + "v1fv_reliable": 0.5, + "v2fv_reliable": 0.5, + "v1_fir_sel": 1, + "v1_band": [0.042, 0.14], + "v1_iir_coe": [-265, 686, 512], + "v1_fir_coe": [-124, 0, 124], + "v2_band": [0.055, 0.125], + "v2_iir_coe": [-325, 724, 512], + "v2_fir_coe": [-94, 0, 94], + "h1_band": [0.042, 0.14], + "h1_iir1_coe": [512, 557, -276, 460, 0, -460], + "h1_iir2_coe": [100, 870, -399, 191, 0, -191], + "h2_band": [0.055, 0.125], + "h2_iir1_coe": [415, 648, -344, 403, 0, -403], + "h2_iir2_coe": [96, 854, -409, 156, 0, -156], + "ldg_en": 0, + "ve_ldg_lumth_l": 64, + "ve_ldg_gain_l": 28, + "ve_ldg_gslp_l": 1286, + "ve_ldg_lumth_h": 185, + "ve_ldg_gain_h": 8, + "ve_ldg_gslp_h": 1400, + "ho_ldg_lumth_l": 64, + "ho_ldg_gain_l": 28, + "ho_ldg_gslp_l": 1286, + "ho_ldg_lumth_h": 185, + "ho_ldg_gain_h": 8, + "ho_ldg_gslp_h": 1400, + "v_fv_thresh": 4, + "h_fv_thresh": 4, + "highlit_thresh": 912, + "v_fv_ratio": 0.5 + }], + "meascfg_tbl_len": 1 + } + }, + "gain_v2": { + "Version": "V2", + "TuningPara": { + "hdrgain_ctrl_enable": 1, + "Setting": [{ + "SNR_Mode": "LSNR", + "Sensor_Mode": "lcg", + "Tuning_ISO": [{ + "iso": 50, + "hdr_gain_scale_s": 1, + "hdr_gain_scale_m": 1 + }], + "Tuning_ISO_len": 1 + }], + "Setting_len": 1 + } + }, + "csm": { + "TuningPara": { + "op_mode": "RK_AIQ_OP_MODE_AUTO", + "full_range": 1, + "y_offset": 0, + "c_offset": 0, + "coeff": [0, 0, 0, 0, 0, 0, 0, 0, 0] + } + }, + "cgc": { + "TuningPara": { + "op_mode": "RK_AIQ_OP_MODE_AUTO", + "cgc_ratio_en": 0, + "cgc_yuv_limit": 0 + } + } + } + }], + "sub_scene_len": 1 + }], + "main_scene_len": 1, + "uapi": [], + "uapi_len": 0, + "sys_static_cfg": { + "algoSwitch": { + "enable": 0, + "disable_algos": ["DISABLE_AF"], + "disable_algos_len": 1 + } + } +} \ No newline at end of file diff --git a/project/app/rkipc/rkipc/common/network/network.c b/project/app/rkipc/rkipc/common/network/network.c index 6863fac75..c11d71dcf 100644 --- a/project/app/rkipc/rkipc/common/network/network.c +++ b/project/app/rkipc/rkipc/common/network/network.c @@ -696,6 +696,13 @@ int rk_network_get_cable_state() { ifinfo = NLMSG_DATA(nh); if_indextoname(ifinfo->ifi_index, name); + if (strcmp(name, "usb0") == 0) { + continue; + } + if (strcmp(name, "wlan0") == 0) { + continue; + } + LOG_INFO("\n[%s] link %s\n", name, (ifinfo->ifi_flags & IFF_LOWER_UP) ? "up" : "down"); memset(cmd1, 0, 32); diff --git a/project/app/rkipc/rkipc/src/rv1106_ipc/CMakeLists.txt b/project/app/rkipc/rkipc/src/rv1106_ipc/CMakeLists.txt index a2dde8941..35a15a7cf 100644 --- a/project/app/rkipc/rkipc/src/rv1106_ipc/CMakeLists.txt +++ b/project/app/rkipc/rkipc/src/rv1106_ipc/CMakeLists.txt @@ -66,6 +66,7 @@ add_executable(${PROJECT_NAME} ${SRCS}) target_link_libraries(${PROJECT_NAME} pthread rockit rockchip_mpp rkaiq rtsp rkaudio_detect aec_bf_process wpa_client m rkmuxer freetype rockiva iconv rknnmrt rga stdc++ rksysutils rkaudio) install(TARGETS ${PROJECT_NAME} RUNTIME DESTINATION bin) +install(FILES rkipc-mia1321-100w.ini DESTINATION share) install(FILES rkipc-300w.ini DESTINATION share) install(FILES rkipc-400w.ini DESTINATION share) install(FILES rkipc-500w.ini DESTINATION share) diff --git a/project/app/rkipc/rkipc/src/rv1106_ipc/RkLunch.sh b/project/app/rkipc/rkipc/src/rv1106_ipc/RkLunch.sh index 2d1aafcda..d41c54353 100644 --- a/project/app/rkipc/rkipc/src/rv1106_ipc/RkLunch.sh +++ b/project/app/rkipc/rkipc/src/rv1106_ipc/RkLunch.sh @@ -73,6 +73,10 @@ post_chk() { default_rkipc_ini=/tmp/rkipc-factory-config.ini if [ ! -f "/oem/usr/share/rkipc.ini" ]; then + lsmod | grep mia1321 + if [ $? -eq 0 ]; then + ln -s -f /oem/usr/share/rkipc-mia1321-100w.ini $default_rkipc_ini + fi lsmod | grep mis5001 if [ $? -eq 0 ]; then ln -s -f /oem/usr/share/rkipc-mis5001-500w.ini $default_rkipc_ini @@ -126,6 +130,24 @@ post_chk() { rk_mpi_ao_test -i /oem/usr/share/speaker_test.wav --sound_card_name=hw:0,0 --device_ch=2 --device_rate=8000 --input_rate=8000 --input_ch=2 --set_volume 50 fi + csi_unite=$(( $(luckfox-config get_csi_unite) )) + if [ -z csi_unite ]; then + csi_unite=0 + fi + if lsmod | grep 'imx415' | awk '{print $3}' | grep -w 1; then + if [ $csi_unite == "0" ]; then + luckfox-config set_csi_unite 1 + echo "[rkipc] Set rockchip,unite to 1; rkipc requires a reboot to function properly." + return + fi + else + if [ $csi_unite == "1" ]; then + luckfox-config set_csi_unite 0 + echo "[rkipc] Set rockchip,unite to 0; rkipc requires a reboot to function properly." + return + fi + fi + if [ -d "/oem/usr/share/iqfiles" ]; then rkipc -a /oem/usr/share/iqfiles & else diff --git a/project/app/rkipc/rkipc/src/rv1106_ipc/rkipc-800w.ini b/project/app/rkipc/rkipc/src/rv1106_ipc/rkipc-800w.ini index 0c5edd03a..7a3c727e4 100755 --- a/project/app/rkipc/rkipc/src/rv1106_ipc/rkipc-800w.ini +++ b/project/app/rkipc/rkipc/src/rv1106_ipc/rkipc-800w.ini @@ -1,5 +1,5 @@ [audio.0] -enable = 1 +enable = 0 card_name = hw:0,0 encode_type = G711A format = S16 @@ -19,14 +19,14 @@ enable_aiq = 1 enable_vo = 0 vo_dev_id = 3 ; 0 is hdmi, 3 is mipi enable_ivs = 1 -enable_jpeg = 1 +enable_jpeg = 0 enable_venc_0 = 1 enable_venc_1 = 0 enable_venc_2 = 0 -enable_npu = 1 +enable_npu = 0 npu_fps = 10 enable_rtsp = 1 -enable_rtmp = 1 +enable_rtmp = 0 rotation = 0 ; available value:0 90 180 270 [video.0] diff --git a/project/app/rkipc/rkipc/src/rv1106_ipc/rkipc-mia1321-100w.ini b/project/app/rkipc/rkipc/src/rv1106_ipc/rkipc-mia1321-100w.ini new file mode 100644 index 000000000..04641f2b4 --- /dev/null +++ b/project/app/rkipc/rkipc/src/rv1106_ipc/rkipc-mia1321-100w.ini @@ -0,0 +1,376 @@ +[audio.0] +enable = 0 +card_name = hw:0,0 +encode_type = G711A +format = S16 +sample_rate = 8000 +channels = 1 +frame_size = 1152 +bit_rate = 16000 +input = mic_in +volume = 50 +enable_aed = 0 +enable_bcd = 0 +enable_vqe = 1 +vqe_cfg = /oem/usr/share/vqefiles/config_aivqe.json + +[video.source] +enable_aiq = 1 +enable_vo = 0 +vo_dev_id = 3 ; 0 is hdmi, 3 is mipi +enable_ivs = 0 +enable_jpeg = 0 +enable_venc_0 = 1 +enable_venc_1 = 0 +enable_venc_2 = 0 +enable_npu = 0 +npu_fps = 0 +enable_rtsp = 1 +enable_rtmp = 0 +rotation = 0 ; available value:0 90 180 270 + +[video.0] +buffer_size = 691200 ; w * h / 2 +buffer_count = 4 +enable_refer_buffer_share = 1 +stream_type = mainStream +video_type = compositeStream +max_width = 1280 +max_height = 1080 +width = 1280 +height = 1080 +rc_mode = CBR +rc_quality = high +src_frame_rate_den = 1 +src_frame_rate_num = 60 +dst_frame_rate_den = 1 +dst_frame_rate_num = 60 +target_rate = 0 +mid_rate = 2048 +max_rate = 4096 +min_rate = 0 +output_data_type = H.265 +smart = close +h264_profile = high +gop = 50 +smartp_viridrlen = 25 +gop_mode = normalP +stream_smooth = 50 +enable_motion_deblur = 1 +motion_deblur_strength = 3 +enable_motion_static_switch = 0 +frame_min_i_qp = 26 +frame_min_qp = 28 +frame_max_i_qp = 51 +frame_max_qp = 51 +scalinglist = 0 +enable_debreath_effect = 0 +debreath_effect_strength = 16 +thrd_i = 0,0,0,0,3,3,5,5,8,8,8,15,15,20,25,25 +thrd_p = 0,0,0,0,3,3,5,5,8,8,8,15,15,20,25,25 +aq_step_i = -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,7,8 +aq_step_p = -8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,7,8 +qbias_enable = 1 +qbias_i = 171 +qbias_p = 85 +flt_str_i = 0 +flt_str_p = 0 +cu_dqp = 1 +anti_ring = 2 +anti_line = 2 +lambds = 4 + +[video.1] +max_width = 704 +max_height = 576 +width = 704 +height = 576 + +[video.2] +max_width = 960 +max_height = 540 +width = 960 +height = 540 + +[ivs] +smear = 0 +weightp = 0 +md = 1 +od = 0 +md_sensibility = 3 ;available: 1 2 3,max 3 + +[video.jpeg] +width = 1280 +height = 1080 +jpeg_buffer_size = 1048576 ; 1024KB +jpeg_qfactor = 70 +enable_cycle_snapshot = 0 +snapshot_interval_ms = 1000 + +[isp] +scenario = normal ; normal or custom1 +init_form_ini = 1 +normal_scene = day + +; isp.0 +[isp.0.adjustment] +contrast = 50 +brightness = 50 +saturation = 50 +sharpness = 50 +fps = 60 +hue = 50 + +[isp.0.enhancement] +noise_reduce_mode = close +denoise_level = 50 +spatial_denoise_level = 50 +temporal_denoise_level = 50 +dehaze = close +dehaze_level = 0 +dis = close +gray_scale_mode = [0-255] +distortion_correction = close +ldch_level = 0 + +[isp.0.video_adjustment] +image_flip = close +scene_mode = indoor +power_line_frequency_mode = PAL(50HZ) + +[storage] +mount_path = /userdata +free_size_del_min = 500; MB +free_size_del_max = 1000; MB +num_limit_enable = 1; limit by file num + +[storage.0] +enable = 0 +folder_name = video0 +file_format = mp4 ; flv,ts +file_duration = 60 +video_quota = 30 +file_max_num = 300 + +[storage.1] +enable = 0 +folder_name = video1 +file_format = mp4 ; flv,ts +file_duration = 60 +video_quota = 30 +file_max_num = 300 + +[storage.2] +enable = 0 +folder_name = video2 +file_format = mp4 ; flv,ts +file_duration = 60 +video_quota = 30 +file_max_num = 300 + +[system.device_info] +deivce_name = RK IP Camera +telecontrol_id = 88 +model = RK-003 +serial_number = RK-003-A +firmware_version = V0.2.6 build 202108 +encoder_version = V1.0 build 202108 +web_version = V2.12.2 build 202108 +plugin_version = V1.0.0.0 +channels_number = 1 +hard_disks_number = 1 +alarm_inputs_number = 0 +alarm_outputs_number = 0 +firmware_version_info = CP-3-B +manufacturer = Rockchip +hardware_id = c3d9b8674f4b94f6 +user_num = 1 + +[capability.video] +0 = {"disabled":[{"name":"sStreamType","options":{"subStream":{"sSmart":"close"},"thirdStream":{"sSmart":"close"}},"type":"disabled/limit"},{"name":"sRCMode","options":{"CBR":{"sRCQuality":null}},"type":"disabled"},{"name":"sOutputDataType","options":{"H.265":{"sH264Profile":null}},"type":"disabled"},{"name":"unspport","options":{"iStreamSmooth":null,"sVideoType":null},"type":"disabled"}],"dynamic":{"sSmart":{"open":{"iMinRate":{"dynamicRange":{"max":"iMaxRate","maxRate":1,"min":"iMaxRate","minRate":0.125},"type":"dynamicRange"}}},"sStreamType":{"mainStream":{"iMaxRate":{"options":[256,512,1024,2048,3072,4096,6144],"type":"options"},"sResolution":{"options":["2880*1616","1920*1080","1280*720","960*540","640*360","320*240"],"type":"options"}},"subStream":{"iMaxRate" +1 = :{"options":[128,256,512],"type":"options"},"sResolution":{"options":["704*576","640*480","352*288","320*240"],"type":"options"}},"thirdStream":{"iMaxRate":{"options":[256,512],"type":"options"},"sResolution":{"options":["416*416"],"type":"options"}}}},"layout":{"encoder":["sStreamType","sVideoType","sResolution","sRCMode","sRCQuality","sFrameRate","sOutputDataType","sSmart","sH264Profile","sGOPMode","iMaxRate","iGOP","iStreamSmooth"]},"static":{"iGOP":{"range":{"max":400,"min":1},"type":"range"},"iStreamSmooth":{"range":{"max":100,"min":1,"step":1},"type":"range"},"sFrameRate":{"dynamicRange":{"max":"sFrameRateIn","maxRate":1},"options":["1/2","1","2","4","6","8","10","12","14","16","18","20","25","30"],"type":"options/dynamicRange"},"sH264Profile":{"options":["high","main","baseline"],"type":"options"},"sOutputDataType":{"options" +2 = :["H.264","H.265"],"type":"options"},"sRCMode":{"options":["CBR","VBR"],"type":"options"},"sRCQuality":{"options":["lowest","lower","low","medium","high","higher","highest"],"type":"options"},"sGOPMode":{"options":["normalP","smartP"],"type":"options"},"sSmart":{"options":["open","close"],"type":"options"},"sStreamType":{"options":["mainStream","subStream","thirdStream"],"type":"options"},"sVideoType":{"options":["videoStream","compositeStream"],"type":"options"}}} + +[capability.image_adjustment] +0 = {"layout":{"image_adjustment":["iBrightness","iContrast","iSaturation","iSharpness","iHue"]},"static":{"iBrightness":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iContrast":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iHue":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iSaturation":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iSharpness":{"range":{"max":100,"min":0,"step":1},"type":"range"}}} + +[capability.image_blc] +0 = {"disabled":[{"name":"sHLC","options":{"open":{"sBLCRegion":null}},"type":"disabled"},{"name":"sBLCRegion","options":{"open":{"iDarkBoostLevel":null,"iHLCLevel":null,"sHLC":null}},"type":"disabled"}],"dynamic":{"sBLCRegion":{"open":{"iBLCStrength":{"range":{"max":100,"min":0,"step":1},"type":"range"}}},"sHDR":{"HDR2":{"iHDRLevel":{"options":[1,2,3,4],"type":"options"}},"close":{"sBLCRegion":{"options":["close","open"],"type":"options"},"sHLC":{"options" +1 = :["close","open"],"type":"options"}}},"sHLC":{"open":{"iDarkBoostLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iHLCLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}}},"sWDR":{"open":{"iWDRLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}}}},"layout":{"image_blc":["sHDR","iHDRLevel","sBLCRegion","iBLCStrength","sHLC","iHLCLevel"]},"static":{"sHDR":{"options":["close","HDR2"],"type":"options"}}} + +[capability.image_enhancement] +0 = {"dynamic":{"sDehaze":{"open":{"iDehazeLevel":{"range":{"max":10,"min":0,"step":1},"type":"range"}}},"sDistortionCorrection":{"FEC":{"iFecLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}},"LDCH":{"iLdchLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}}},"sNoiseReduceMode":{"2dnr":{"iSpatialDenoiseLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}},"3dnr":{"iTemporalDenoiseLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}},"mixnr":{"iSpatialDenoiseLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iTemporalDenoiseLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}}}},"layout" +1 = :{"image_enhancement":["sNoiseReduceMode","iSpatialDenoiseLevel","iTemporalDenoiseLevel","sDehaze","iDehazeLevel","sGrayScaleMode","sDistortionCorrection","iLdchLevel","iFecLevel"]},"static":{"sDIS":{"options":["open","close"],"type":"options"},"sDehaze":{"options":["open","close","auto"],"type":"options"},"sDistortionCorrection":{"options":["LDCH","close"],"type":"options"},"sFEC":{"options":["open","close"],"type":"options"},"sGrayScaleMode":{"options":["[0-255]","[16-235]"],"type":"options"},"sNoiseReduceMode":{"options":["close","2dnr","3dnr","mixnr"],"type":"options"}}} + +[capability.image_exposure] +0 = {"dynamic":{"sExposureMode":{"auto":{"iAutoIrisLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}},"manual":{"sExposureTime":{"options":["1","1/3","1/6","1/12","1/25","1/50","1/100","1/150","1/200","1/250","1/500","1/750","1/1000","1/2000","1/4000","1/10000","1/100000"],"type":"options"},"sGainMode":{"options":["auto","manual"],"type":"options"}}},"sGainMode":{"manual":{"iExposureGain":{"range":{"max":100,"min":1,"step":1},"type":"range"}}}},"layout":{"image_exposure":["sExposureMode","sExposureTime","sGainMode","iExposureGain","iFPS"]},"static":{"sExposureMode":{"options":["auto","manual"],"type":"options"},"iFPS":{"range":{"max":30,"min":0,"step":1},"type":"range"}}} + +[capability.image_night_to_day] +0 = {"disabled":[{"name":"sNightToDay","options":{"day":{"iLightBrightness":null,"sFillLightMode":null},"night":{"iDarkBoostLevel":null,"iHDRLevel":null,"iHLCLevel":null,"sHDR":null,"sHLC":"close"}},"type":"disabled"}],"dynamic":{"sNightToDay":{"auto":{"iNightToDayFilterLevel":{"options":[0,1,2,3,4,5,6,7],"type":"options"},"iNightToDayFilterTime":{"range":{"max":10,"min":3,"step":1},"type":"range"}},"schedule":{"sDawnTime":{"input":"time","type":"input"},"sDuskTime":{"input":"time","type":"input"}}},"sOverexposeSuppress":{"open" +1 = :{"sOverexposeSuppressType":{"options":["auto","manual"],"type":"options"}}},"sOverexposeSuppressType":{"manual":{"iDistanceLevel":{"range":{"max":100,"min":0,"step":1},"type":"range"}}}},"layout":{"image_night_to_day":["sNightToDay","iNightToDayFilterLevel","iNightToDayFilterTime","sDawnTime","sDuskTime","sFillLightMode","iLightBrightness"]},"static":{"iLightBrightness":{"range":{"max":100,"min":0,"step":10},"type":"range"},"sNightToDay":{"options":["day","night"],"type":"options"},"sFillLightMode":{"type":"options","options":["IR"]}}} + +[capability.image_video_adjustment] +0 = {"layout":{"image_video_adjustment":["sPowerLineFrequencyMode","sImageFlip","iImageRotation"]},"static":{"sImageFlip":{"options":["close","flip","mirror","centrosymmetric"],"type":"options"},"sPowerLineFrequencyMode":{"options":["PAL(50HZ)","NTSC(60HZ)"],"type":"options"},"sSceneMode":{"options":["indoor","outdoor"],"type":"options"},"iImageRotation":{"options":[0,90,180,270],"type":"options"}}} + +[capability.image_white_blance] +0 = {"dynamic":{"sWhiteBlanceStyle":{"manualWhiteBalance":{"iWhiteBalanceBlue":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iWhiteBalanceGreen":{"range":{"max":100,"min":0,"step":1},"type":"range"},"iWhiteBalanceRed":{"range":{"max":100,"min":0,"step":1},"type":"range"}}}},"layout":{"image_white_blance":["sWhiteBlanceStyle","iWhiteBalanceRed","iWhiteBalanceGreen","iWhiteBalanceBlue"]},"static":{"sWhiteBlanceStyle":{"options":["manualWhiteBalance","autoWhiteBalance","lockingWhiteBalance","fluorescentLamp","incandescent","warmLight","naturalLight"],"type":"options"}}} + +[user.0] +user_name = admin +password = YWRtaW4= +user_level = 1 ; administrator=0 operator=1 user=2 + +[osd.common] +enable_osd = 1 +is_presistent_text = 1 +attribute = transparent/not-flashing +font_size = 32 +font_color_mode = customize +font_color = fff799 +alignment = customize +boundary = 0 +font_path = /oem/usr/share/simsun_en.ttf +normalized_screen_width = 704 +normalized_screen_height = 480 + +[osd.0] +type = channelName +enabled = 0 +position_x = 1104 +position_y = 640 +display_text = Camera 01 + +[osd.1] +type = dateTime +enabled = 1 +position_x = 16 +position_y = 16 +date_style = CHR-YYYY-MM-DD +time_style = 24hour +display_week_enabled = 0 + +[osd.2] +type = character +enabled = 0 +position_x = 0 +position_y = 0 +display_text = null + +[osd.3] +type = character +enabled = 0 +position_x = 0 +position_y = 0 +display_text = null + +[osd.4] +type = privacyMask +enabled = 0 +position_x = 0 +position_y = 0 +width = 0 +height = 0 + +[osd.5] +type = privacyMask +enabled = 0 +position_x = 0 +position_y = 0 +width = 0 +height = 0 + +[osd.6] +type = image +enabled = 0 +position_x = 16 +position_y = 640 +image_path = /userdata/image.bmp + +[event.regional_invasion] +enabled = 1 +position_x = 0 +position_y = 0 +width = 700 +height = 560 +proportion = 1 +sensitivity_level = 90 +time_threshold = 1 +rockiva_model_type = small ;big medium small + +[roi.0] +stream_type = mainStream +id = 1 +enabled = 0 +name = test +position_x = 0 +position_y = 0 +width = 0 +height = 0 +quality_level = 3 + +[roi.1] +stream_type = mainStream +id = 2 +enabled = 0 +name = test +position_x = 0 +position_y = 0 +width = 0 +height = 0 +quality_level = 3 + +[roi.2] +stream_type = subStream +id = 1 +enabled = 0 +name = test +position_x = 0 +position_y = 0 +width = 0 +height = 0 +quality_level = 3 + +[roi.3] +stream_type = subStream +id = 2 +enabled = 0 +name = test +position_x = 0 +position_y = 0 +width = 0 +height = 0 +quality_level = 3 + +[roi.4] +stream_type = thirdStream +id = 1 +enabled = 0 +name = test +position_x = 0 +position_y = 0 +width = 0 +height = 0 +quality_level = 3 + +[roi.5] +stream_type = thirdStream +id = 2 +enabled = 0 +name = test +position_x = 0 +position_y = 0 +width = 0 +height = 0 +quality_level = 3 + +[region_clip.1] +enabled = 0 +position_x = 0 +position_y = 0 +width = 640 +height = 480 + +[network.ntp] +enable = 1 +refresh_time_s = 60 +ntp_server = 119.28.183.184 diff --git a/project/build.sh b/project/build.sh index a6eecf642..3f87c73bc 100755 --- a/project/build.sh +++ b/project/build.sh @@ -158,7 +158,8 @@ function choose_target_board() { "RV1106_Luckfox_Pico_Pi" "RV1106_Luckfox_Pico_Pi_W" "RV1106_Luckfox_Pico_86Panel" - "RV1106_Luckfox_Pico_86Panel_W") + "RV1106_Luckfox_Pico_86Panel_W" + "RV1106_Luckfox_Pico_Zero") local LF_BOOT_MEDIA=("SD_CARD" "SPI_NAND" "EMMC") local LF_SYSTEM=("Buildroot" "Custom") local cnt=0 space8=" " @@ -192,6 +193,8 @@ function choose_target_board() { LUNCH_NUM=$((LUNCH_NUM + 1)) echo "${space8}${space8}[${LUNCH_NUM}] RV1106_Luckfox_Pico_86Panel_W" LUNCH_NUM=$((LUNCH_NUM + 1)) + echo "${space8}${space8}[${LUNCH_NUM}] RV1106_Luckfox_Pico_Zero" + LUNCH_NUM=$((LUNCH_NUM + 1)) echo "${space8}${space8}[${LUNCH_NUM}] custom" read -p "Which would you like? [0~${LUNCH_NUM}][default:0]: " HW_INDEX @@ -276,7 +279,7 @@ function choose_target_board() { range_sd_card=(0) range_sd_card_spi_nand=(1 2 3 4) - range_emmc=(5 6 7 8 9 10) + range_emmc=(5 6 7 8 9 10 11) if __IS_IN_ARRAY "$HW_INDEX" "${range_sd_card[@]}"; then echo "${space8}${space8}[0] SD_CARD" diff --git a/project/cfg/BoardConfig_IPC/BoardConfig-EMMC-Buildroot-RV1106_Luckfox_Pico_Zero-IPC.mk b/project/cfg/BoardConfig_IPC/BoardConfig-EMMC-Buildroot-RV1106_Luckfox_Pico_Zero-IPC.mk new file mode 100755 index 000000000..2939794f1 --- /dev/null +++ b/project/cfg/BoardConfig_IPC/BoardConfig-EMMC-Buildroot-RV1106_Luckfox_Pico_Zero-IPC.mk @@ -0,0 +1,129 @@ +#!/bin/bash + +################################################# +# Board Config +################################################# +export LF_ORIGIN_BOARD_CONFIG=BoardConfig-EMMC-Buildroot-RV1106_Luckfox_Pico_Zero-IPC.mk +# Target CHIP +export RK_CHIP=rv1106 + +# app config +export RK_APP_TYPE=RKIPC_RV1106 + +# Config CMA size in environment +export RK_BOOTARGS_CMA_SIZE="100M" + +# Kernel dts +export RK_KERNEL_DTS=rv1106g-luckfox-pico-zero.dts + +################################################# +# BOOT_MEDIUM +################################################# + +# Target boot medium +export RK_BOOT_MEDIUM=emmc + +# Uboot defconfig fragment +export RK_UBOOT_DEFCONFIG_FRAGMENT="rk-emmc.config" + +# specify post.sh for delete/overlay files +# export RK_PRE_BUILD_OEM_SCRIPT=rv1103-spi_nor-post.sh + +# config partition in environment +# RK_PARTITION_CMD_IN_ENV format: +# [,] +# := [@](part-name) +# Note: +# If the first partition offset is not 0x0, it must be added. Otherwise, it needn't adding. +export RK_PARTITION_CMD_IN_ENV="32K(env),512K@32K(idblock),256K(uboot),32M(boot),512M(oem),256M(userdata),6G(rootfs)" + +# config partition's filesystem type (squashfs is readonly) +# emmc: squashfs/ext4 +# nand: squashfs/ubifs +# spi nor: squashfs/jffs2 +# RK_PARTITION_FS_TYPE_CFG format: +# AAAA:/BBBB/CCCC@ext4 +# AAAA ----------> partition name +# /BBBB/CCCC ----> partition mount point +# ext4 ----------> partition filesystem type +export RK_PARTITION_FS_TYPE_CFG=rootfs@IGNORE@ext4,userdata@/userdata@ext4,oem@/oem@ext4 + +# config filesystem compress (Just for squashfs or ubifs) +# squashfs: lz4/lzo/lzma/xz/gzip, default xz +# ubifs: lzo/zlib, default lzo +# export RK_SQUASHFS_COMP=xz +# export RK_UBIFS_COMP=lzo + +################################################# +# TARGET_ROOTFS +################################################# + +# Target rootfs +export LF_TARGET_ROOTFS=buildroot + +# Buildroot defconfig +export RK_BUILDROOT_DEFCONFIG=luckfox_pico_w_defconfig + +################################################# +# Defconfig +################################################# + +# Target arch +export RK_ARCH=arm + +# Target Toolchain Cross Compile +export RK_TOOLCHAIN_CROSS=arm-rockchip830-linux-uclibcgnueabihf + +#misc image +export RK_MISC=wipe_all-misc.img + +# Uboot defconfig +export RK_UBOOT_DEFCONFIG=luckfox_rv1106_uboot_defconfig + +# Kernel defconfig +export RK_KERNEL_DEFCONFIG=luckfox_rv1106_linux_defconfig + +# Kernel defconfig fragment +export RK_KERNEL_DEFCONFIG_FRAGMENT=rv1106-bt.config + +# Config sensor IQ files +# RK_CAMERA_SENSOR_IQFILES format: +# "iqfile1 iqfile2 iqfile3 ..." +# ./build.sh media and copy /output/out/media_out/isp_iqfiles/$RK_CAMERA_SENSOR_IQFILES +#export RK_CAMERA_SENSOR_IQFILES="sc4336_OT01_40IRC_F16.json sc3336_CMK-OT2119-PC1_30IRC-F16.json mis5001_CMK-OT2115-PC1_30IRC-F16.json" +#export RK_CAMERA_SENSOR_IQFILES="sc4336_OT01_40IRC_F16.json sc3336_CMK-OT2119-PC1_30IRC-F16.json sc530ai_CMK-OT2115-PC1_30IRC-F16.json" +export RK_CAMERA_SENSOR_IQFILES="mia1321_MIA1321_30IRC-F16.json imx415_CMK-OT2022-PX1_IR0147-36IRC-8M-F20.json" + +# Config sensor lens CAC calibrattion bin files +#export RK_CAMERA_SENSOR_CAC_BIN="CAC_sc4336_OT01_40IRC_F16" +#export RK_CAMERA_SENSOR_CAC_BIN="CAC_sc4336_OT01_40IRC_F16 CAC_sc530ai_CMK-OT2115-PC1_30IRC-F16" + +# build ipc web backend +#export RK_APP_IPCWEB_BACKEND=y + +# enable install app to oem partition +export RK_BUILD_APP_TO_OEM_PARTITION=y + +# enable rockchip test +export RK_ENABLE_ROCKCHIP_TEST=y + +# enable rockchip wifi +export RK_ENABLE_WIFI=y +export RK_ENABLE_WIFI_CHIP=AIC8800DC + +# config wifi ssid and passwd +export LF_WIFI_SSID="Your wifi ssid" +export LF_WIFI_PSK="Your wifi password" + +################################################# +# PRE and POST +################################################# + +# specify pre.sh for delete/overlay files +export RK_PRE_BUILD_OEM_SCRIPT=luckfox-buildroot-oem-pre.sh + +# specify post.sh for delete/overlay files +export RK_PRE_BUILD_USERDATA_SCRIPT=luckfox-userdata-pre.sh + +# declare overlay directory +export RK_POST_OVERLAY="overlay-luckfox-config overlay-luckfox-buildroot-init overlay-luckfox-buildroot-shadow" diff --git a/project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-config/usr/bin/luckfox-config b/project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-config/usr/bin/luckfox-config index bcefc9588..8742df72b 100755 --- a/project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-config/usr/bin/luckfox-config +++ b/project/cfg/BoardConfig_IPC/overlay/overlay-luckfox-config/usr/bin/luckfox-config @@ -201,6 +201,34 @@ function luckfox_pico_pi_pin_diagram_file() { EOF } +function luckfox_pico_zero_pin_diagram_file() { + cat >$LUCKFOX_PIN_DIAGRAM_FILE <; }; + +&{/rkisp@ffa00000}{ + rockchip,unite = <$unite_state>; +}; " else local i2c_content=" @@ -2060,6 +2101,8 @@ function luckfox_csi_app() { # update cfg luckfox_set_pin_cfg "CSI_ENABLE" "$action" luckfox_set_pin_parameter "CSI_ENABLE" "$action" + luckfox_set_pin_cfg "CSI_UNITE_ENABLE" "$action" + luckfox_set_pin_parameter "CSI_UNITE_ENABLE" "$action" luckfox_set_pin_mark "I2C4_M0_SCL" 0 luckfox_set_pin_mark "I2C4_M0_SDA" 0 @@ -2877,7 +2920,8 @@ function luckfox_show_menu() { esac done # Only support Luckfox Pico Ultra /Luckfox Pico Ultra W - elif [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Ultra" ] || [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Ultra W" ]; then + elif [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Ultra" ] || [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Ultra W" ] || + [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Zero" ]; then while true; do option=$(dialog --title "$LUCKFOX_CHIP_MODEL Config" \ --menu "Choose an option" 80 50 6 \ @@ -2894,21 +2938,41 @@ function luckfox_show_menu() { esac done else - while true; do - option=$(dialog --title "$LUCKFOX_CHIP_MODEL Config" \ - --menu "Choose an option" 80 50 6 \ - 1 "Compatible Devices" \ - 2 "Advanced Options" \ - 3 "About Luckfox" \ - 2>&1 >/dev/tty) + if [ "$LUCKFOX_CHIP_MEDIA_CLASS" == "sdmmc" ]; then + while true; do + option=$(dialog --title "$LUCKFOX_CHIP_MODEL Config" \ + --menu "Choose an option" 80 50 6 \ + 1 "Compatible Devices" \ + 2 "Advanced Options" \ + 3 "Backup" \ + 4 "About Luckfox" \ + 2>&1 >/dev/tty) - case $option in - 1) luckfox_compatible_devices ;; - 2) luckfox_advanced_options ;; - 3) luckfox_about ;; - *) luckfox_exit ;; - esac - done + case $option in + 1) luckfox_compatible_devices ;; + 2) luckfox_advanced_options ;; + 3) luckfox_backup ;; + 4) luckfox_about ;; + *) luckfox_exit ;; + esac + done + else + while true; do + option=$(dialog --title "$LUCKFOX_CHIP_MODEL Config" \ + --menu "Choose an option" 80 50 6 \ + 1 "Compatible Devices" \ + 2 "Advanced Options" \ + 3 "About Luckfox" \ + 2>&1 >/dev/tty) + + case $option in + 1) luckfox_compatible_devices ;; + 2) luckfox_advanced_options ;; + 3) luckfox_about ;; + *) luckfox_exit ;; + esac + done + fi fi } @@ -3028,11 +3092,12 @@ function luckfox_advanced_options() { function luckfox_backup() { option=$(dialog --title "Advanced Options" \ --menu "Choose an option" 80 50 6 \ - 1 "rootfs" \ + 0 "rootfs" \ 2>&1 >/dev/tty) - if [ $option == 1 ]; then - if [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Pi" ] || [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Pi W" ]; then + if [ "$option" == "0" ]; then + if [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Pi" ] || [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Pi W" ] || \ + [ "$LUCKFOX_CHIP_MODEL" == "Luckfox Pico Zero" ]; then media_class=$(dialog --menu "Select Backup Image Location" 80 50 6 \ 0 "local" \ 1 "usb_disk" \ @@ -3043,6 +3108,13 @@ function luckfox_backup() { 0 "local" \ 1 "usb_disk" \ 2>&1 >/dev/tty) + else + if [ "$LUCKFOX_CHIP_MEDIA_CLASS" == "sdmmc" ]; then + media_class=$(dialog --menu "Select Backup Image Location" 80 50 6 \ + 0 "local" \ + 1 "usb_disk" \ + 2>&1 >/dev/tty) + fi fi luckfox_rootfs_BACKUP "$media_class" else @@ -3279,6 +3351,7 @@ function luckfox_USB() { function luckfox_CSI() { local csi_enable + local unite_enable csi_enable=$(dialog --menu "CSI Enable Config" 10 40 2 \ 0 "disable" \ 1 "enable" \ @@ -3286,7 +3359,18 @@ function luckfox_CSI() { if [ -z "$csi_enable" ]; then luckfox_advanced_options fi - luckfox_csi_app "$csi_enable" + + if [ "$csi_enable" == 1 ]; then + unite_enable=$(dialog --menu "CSI Unite Mode Config(for 3840x2160 input)" 10 40 2 \ + 0 "disable" \ + 1 "enable" \ + 2>&1 >/dev/tty) + if [ -z "$unite" ]; then + luckfox_advanced_options + fi + fi + + luckfox_csi_app "$csi_enable" "$unite_enable" dialog --msgbox "CSI Effective after restart" 10 30 echo "Set CSI enable status : $csi_enable." >>"$LUCKFOX_CHANGE_TXT" luckfox_advanced_options @@ -3492,13 +3576,22 @@ function luckfox_4G() { 1 "CTCC(ctnet)" \ 2 "CMCC(cmnet)" \ 3 "CUCC(3gwap)" \ + 4 "custom" \ 2>&1 >/dev/tty) - case $card_type in - 1) apn="ctnet" ;; - 2) apn="cmnet" ;; - 3) apn="3gwap" ;; - esac + if [ "$card_type" == 4 ]; then + apn=$(dialog --inputbox "4G Module PPP Mode APN:" 10 30 2>&1 >/dev/tty) + if [ -z "apn" ]; then + dialog --msgbox "Invalid inputs" 10 30 + luckfox_advanced_options + fi + else + case $card_type in + 1) apn="ctnet" ;; + 2) apn="cmnet" ;; + 3) apn="3gwap" ;; + esac + fi fi fi @@ -3520,7 +3613,11 @@ function luckfox_rootfs_BACKUP() { luckfox_result_handle "$LF_ERR" "The rsync is not installed" fi - if [ "$media_class" == 1 ]; then + if [ "$media_class" == 0 ]; then + AVAILABLE_SPACE=$(df -k /mnt | tail -1 | awk '{print $4}') + IMAGE_NAME="/mnt/backup_rootfs.img" + MOUNT_POINT="/mnt/backup_img" + elif [ "$media_class" == 1 ]; then if ! mount | grep "/mnt/udisk"; then luckfox_result_handle "$LF_ERR" "USB disk is not mounted" fi @@ -3535,9 +3632,7 @@ function luckfox_rootfs_BACKUP() { IMAGE_NAME="/mnt/sdcard/backup_rootfs.img" MOUNT_POINT="/mnt/sdcard/backup_img" else - AVAILABLE_SPACE=$(df -k /mnt | tail -1 | awk '{print $4}') - IMAGE_NAME="/mnt/backup_rootfs.img" - MOUNT_POINT="/mnt/backup_img" + luckfox_show_menu fi used_kb=$(df -k / | tail -1 | awk '{print $3}') @@ -3560,7 +3655,10 @@ function luckfox_rootfs_BACKUP() { if mountpoint -q "$MOUNT_POINT"; then umount "$MOUNT_POINT" fi - rm -rf "$MOUNT_POINT" + + if [ -d "$MOUNT_POINT" ]; then + rm -rf "$MOUNT_POINT" + fi mkdir -p "$MOUNT_POINT" { @@ -3590,9 +3688,9 @@ function luckfox_rootfs_BACKUP() { echo 80 echo "Copying rootfs with rsync..." echo "XXX" - rsync -aX --exclude={"/oem","/userdata","/mnt","/tmp","/proc"} / "$MOUNT_POINT" >>"$LOG_FILE" 2>&1 + rsync -aX --exclude={"/oem","/userdata","/sys","/mnt","/tmp","/proc"} / "$MOUNT_POINT" >>"$LOG_FILE" 2>&1 - mkdir -p "$MOUNT_POINT/mnt" "$MOUNT_POINT/tmp" "$MOUNT_POINT/proc" "$MOUNT_POINT/userdata" "$MOUNT_POINT/oem" + mkdir -p "$MOUNT_POINT/sys" "$MOUNT_POINT/mnt" "$MOUNT_POINT/tmp" "$MOUNT_POINT/proc" "$MOUNT_POINT/userdata" "$MOUNT_POINT/oem" echo "XXX" echo 100 @@ -3603,7 +3701,6 @@ function luckfox_rootfs_BACKUP() { dialog --title "Backup Succeeded" --msgbox "The image is saved at $IMAGE_NAME" 10 60 luckfox_show_menu - } ################################################################ @@ -3653,7 +3750,6 @@ elif [ "$1" == "rgb_switch" ]; then echo "****************************************************" echo "***Switch the RGB screen resolution to 720 x 720.***" echo "****************************************************" - luckfox_csi_app 1 luckfox_rgb_app 1 "reset" "30000000" \ "720" "720" \ "44" "46" \ @@ -3666,7 +3762,6 @@ elif [ "$1" == "rgb_switch" ]; then echo "****************************************************" echo "***Switch the RGB screen resolution to 480 x 480.***" echo "****************************************************" - luckfox_csi_app 1 luckfox_rgb_app 1 "reset" "16500000" \ "480" "480" \ "10" "50" \ @@ -3678,7 +3773,6 @@ elif [ "$1" == "rgb_switch" ]; then echo "****************************************************" echo "***Switch the RGB screen resolution to 480 x 480.***" echo "****************************************************" - luckfox_csi_app 1 luckfox_rgb_app 1 "reset" "16500000" \ "480" "480" \ "10" "50" \ @@ -3690,6 +3784,33 @@ elif [ "$1" == "rgb_switch" ]; then else luckfox_result_handle "$RK_ERR" "This Luckchip Pico Model does not support RGB switch." fi +elif [ "$1" == "get_csi_unite" ]; then + LF_GUI_ENABLE=0 + luckfox_config_init + luckfox_update_fdt + + csi_unite_status=$(grep -A 9 "rkisp@ffa00000 {" $LUCKFOX_FDT_DUMP_TXT | grep 'rockchip,unite' | awk '{print $3}' | sed 's/[<>;]//g') + if [ -z "$csi_unite_status" ]; then + csi_unite_status=0 + fi + + echo $(($csi_unite_status)) +elif [ "$1" == "set_csi_unite" ]; then + LF_GUI_ENABLE=0 + luckfox_config_init + + csi_status=$(luckfox_get_pin_mark "CSI_ENABLE") + if [ -z "$csi_status" ]; then + csi_status=1 + fi + + #csi_unite_status=$(luckfox_get_pin_mark "CSI_UNITE_ENABLE") + csi_unite_status="$2" + if [ -z "csi_unite_status" ]; then + csi_unite_status=0 + fi + + luckfox_csi_app "$csi_status" "$csi_unite_status" elif [ -z "$1" ]; then LF_GUI_ENABLE=1 luckfox_config_init diff --git a/sysdrv/drv_ko/insmod_ko.sh b/sysdrv/drv_ko/insmod_ko.sh index 6f9b01944..769c7871a 100644 --- a/sysdrv/drv_ko/insmod_ko.sh +++ b/sysdrv/drv_ko/insmod_ko.sh @@ -14,7 +14,7 @@ __insmod() __rmmod_camera_sensor() { - for item in `echo "imx415 os04a10 sc4336 sc3336 sc530ai gc2053 sc200ai sc401ai sc450ai techpoint mis5001"` + for item in `echo "imx415 os04a10 sc4336 sc3336 sc530ai gc2053 sc200ai sc401ai sc450ai techpoint mis5001 mia1321"` do if lsmod | grep $item | awk '{print $3}' |grep -w 0;then rmmod $item @@ -57,6 +57,7 @@ __insmod sc401ai.ko __insmod sc450ai.ko __insmod techpoint.ko __insmod mis5001.ko +__insmod mia1321.ko __insmod video_rkcif.ko __insmod video_rkisp.ko diff --git a/sysdrv/drv_ko/wifi/insmod_wifi.sh b/sysdrv/drv_ko/wifi/insmod_wifi.sh index d4a139d6b..f34ae1581 100755 --- a/sysdrv/drv_ko/wifi/insmod_wifi.sh +++ b/sysdrv/drv_ko/wifi/insmod_wifi.sh @@ -107,7 +107,8 @@ if [ $? -eq 0 ]; then fi #aic8800 -if [ -n "$(cat /proc/device-tree/model | grep "W")" ]; then +if [ -n "$(cat /proc/device-tree/model | grep "W")" ] || \ +[ -n "$(cat /sys/bus/sdio/devices/*/uevent | grep "C8A1\:C18D")" ]; then insmod cfg80211.ko insmod libarc4.ko insmod ctr.ko diff --git a/sysdrv/source/kernel/arch/arm/boot/dts/rv1106-luckfox-pico-zero-ipc.dtsi b/sysdrv/source/kernel/arch/arm/boot/dts/rv1106-luckfox-pico-zero-ipc.dtsi new file mode 100755 index 000000000..e6dcef6a7 --- /dev/null +++ b/sysdrv/source/kernel/arch/arm/boot/dts/rv1106-luckfox-pico-zero-ipc.dtsi @@ -0,0 +1,445 @@ + +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include "rv1106-evb.dtsi" +#include +#include + +/ { + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk0p7 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0"; + }; + + reserved_memory: reserved-memory { + status = "okay"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + mmc_ecsd: mmc@3f000 { + reg = <0x3f000 0x00001000>; + }; + }; + + acodec_sound: acodec-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rv1106-acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; + + dsm_sound: dsm-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,dsm-sound"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + sndcodec: simple-audio-card,codec { + sound-dai = <&dsm>; + }; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_arm: vdd-arm { + compatible = "regulator-fixed"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work{ + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "activity"; + default-state = "on"; + }; + }; + + out_osc_mia1321: out-osc-mia1321 { + compatible = "fixed-clock"; + clock-output-names = "out-osc-mia1321"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + out_osc_imx415: out-osc-imx415 { + compatible = "fixed-clock"; + clock-output-names = "out-osc-imx415"; + clock-frequency = <37125000>; + #clock-cells = <0>; + }; + + cam_ircut0: cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; +}; + +/***************************** audio ********************************/ +&i2s0_8ch { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&acodec { + #sound-dai-cells = <0>; + status = "okay"; +}; + +/************************* FIQ_DUBUGGER ****************************/ +&fiq_debugger { + rockchip,irq-mode-enable = <1>; + status = "okay"; +}; + +/***************************** USB *********************************/ +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usbdrd { + status = "okay"; +}; + +&usbdrd_dwc3 { + extcon = <&u2phy>; + status = "okay"; +}; + +/***************************** DSM *********************************/ +&dsm { + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +/*************************** CSI *********************************/ +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + //mia1321 + csi_dphy_input0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mia1321_out>; + data-lanes = <1 2>; + }; + + //imx415 + csi_dphy_input1: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out>; + data-lanes = <1 2 3 4>; + }; + + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csi_dphy_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m2_xfer>; + + mia1321: mia1321@60 { + compatible = "imagedesign,mia1321"; + reg = <0x60>; + clocks = <&out_osc_mia1321>; + clock-names = "xvclk"; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_io_1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "MIA1321"; + rockchip,camera-module-lens-name = "30IRC-F16"; + port { + mia1321_out: endpoint { + remote-endpoint = <&csi_dphy_input0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + imx415: imx415@37 { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x37>; + clocks = <&out_osc_imx415>; + clock-names = "xvclk"; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_io_1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-36IRC-8M-F20"; + lens-focus = <&cam_ircut0>; + port { + imx415_out: endpoint { + remote-endpoint = <&csi_dphy_input1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csi_dphy_output>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mipi_pins>; + port { + /* MIPI CSI-2 endpoint */ + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + /* MIPI CSI-2 endpoint */ + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_in>; + }; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port@0 { + isp_in: endpoint { + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +/***************************** ADC ********************************/ +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&tsadc { + status = "okay"; +}; + +/**************************** PINCTRL ******************************/ +// SPI +&spi0 { + pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + spidev@0 { + compatible = "rockchip,spidev"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +// I2C +&i2c1 { + pinctrl-0 = <&i2c1m1_xfer>; +}; +&i2c2 { + pinctrl-0 = <&i2c2m0_xfer>; +}; +&i2c3 { + pinctrl-0 = <&i2c3m0_xfer &i2c3m1_xfer &i2c3m2_xfer>; +}; +&i2c4 { + pinctrl-names = "default", "config"; + pinctrl-0 = <&i2c4m2_xfer>; + pinctrl-1 = <&i2c4m0_xfer &i2c4m1_xfer>; +}; + +// UART +&uart0 { + pinctrl-0 = <&uart0m0_xfer &uart0m1_xfer>; +}; +&uart1 { + pinctrl-0 = <&uart1m1_xfer>; +}; +&uart3 { + + pinctrl-0 = <&uart3m0_xfer &uart3m1_xfer>; +}; +&uart4 { + pinctrl-0 = <&uart4m0_xfer &uart4m1_xfer>; +}; +&uart5 { + pinctrl-0 = <&uart5m1_xfer>; +}; + +// PWM +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; +}; +&pwm1 { + pinctrl-0 = <&pwm1m0_pins &pwm1m1_pins &pwm1m2_pins>; +}; +&pwm2 { + pinctrl-0 = <&pwm2m0_pins &pwm2m1_pins &pwm2m2_pins>; +}; +&pwm3 { + pinctrl-0 = <&pwm3m1_pins &pwm3m2_pins>; +}; +&pwm4 { + pinctrl-0 = <&pwm4m0_pins &pwm4m1_pins &pwm4m2_pins>; +}; +&pwm5 { + pinctrl-0 = <&pwm5m1_pins &pwm5m2_pins>; +}; +&pwm6 { + pinctrl-0 = <&pwm6m1_pins &pwm6m2_pins>; +}; +&pwm7 { + pinctrl-0 = <&pwm7m0_pins &pwm7m1_pins>; +}; +&pwm8 { + pinctrl-0 = <&pwm8m1_pins>; +}; +&pwm9 { + pinctrl-0 = <&pwm9m1_pins>; +}; +&pwm10 { + pinctrl-0 = <&pwm10m1_pins &pwm10m2_pins>; +}; +&pwm11 { + pinctrl-0 = <&pwm11m1_pins &pwm11m2_pins>; +}; + +&pinctrl { + cam { + cam_io_0: cam-io-0 { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + cam_io_1: cam-io-1 { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + spi0 { + spi0m0_clk: spi0m0-clk { + rockchip,pins = <1 RK_PC1 4 &pcfg_pull_none>; + }; + spi0m0_mosi: spi0m0-mosi { + rockchip,pins = <1 RK_PC2 6 &pcfg_pull_none>; + }; + spi0m0_miso: spi0m0-miso { + rockchip,pins = <1 RK_PC3 6 &pcfg_pull_none>; + }; + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = <1 RK_PC0 4 &pcfg_pull_none>; + }; + }; +}; diff --git a/sysdrv/source/kernel/arch/arm/boot/dts/rv1106g-luckfox-pico-zero.dts b/sysdrv/source/kernel/arch/arm/boot/dts/rv1106g-luckfox-pico-zero.dts new file mode 100755 index 000000000..05b351e7f --- /dev/null +++ b/sysdrv/source/kernel/arch/arm/boot/dts/rv1106g-luckfox-pico-zero.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1106.dtsi" +#include "rv1106-luckfox-pico-zero-ipc.dtsi" +#include +#include + +/ { + model = "Luckfox Pico Zero"; + compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1106g3"; + + restart-poweroff { + compatible = "restart-poweroff"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,wake_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +/**********CRU**********/ +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ARMCLK>, + <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>, + <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>, + <&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>, + <&cru HCLK_PMU_ROOT>, <&cru CLK_500M_SRC>; + assigned-clock-rates = + <1188000000>, <700000000>, + <1104000000>, + <400000000>, <200000000>, + <100000000>, <300000000>, + <100000000>, <100000000>, + <200000000>, <700000000>; +}; + +/**********NPU**********/ +&npu { + assigned-clock-rates = <700000000>; +}; + +/**********EMMC**********/ +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + // mmc-hs200-1_8v; + rockchip,default-sample-phase = <90>; + no-sdio; + no-sd; + memory-region-ecsd = <&mmc_ecsd>; + post-power-on-delay-ms = <0>; + status = "okay"; +}; + +&fiq_debugger { + rockchip,irq-mode-enable = <1>; + status = "okay"; +}; + +/**********SDIO-WIFI**********/ +&sdmmc { + max-frequency = <50000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + //non-removable; + rockchip,default-sample-phase = <90>; + // no-sd; + // no-mmc; + supports-sdio; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + status = "okay"; +}; + +&pinctrl{ + sdmmc0{ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <3 RK_PA1 1 &pcfg_pull_up>; + }; + }; +}; + +/**********SD_CARD**********/ +&sdio { + max-frequency = <50000000>; + no-sdio; + no-mmc; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>; + status = "okay"; +}; + +/**********ETH**********/ +&gmac { + status = "disabled"; +}; + +/**********USB**********/ +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "peripheral"; + //dr_mode = "host"; +}; + +/**********RTC**********/ +&rtc { + status = "okay"; +}; + +/**********BT**********/ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&pinctrl { + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/**********SPI**********/ +&spi0 { + status = "disabled"; + spidev@0 { + spi-max-frequency = <50000000>; + }; +}; diff --git a/sysdrv/source/kernel/arch/arm/configs/luckfox_rv1106_linux_defconfig b/sysdrv/source/kernel/arch/arm/configs/luckfox_rv1106_linux_defconfig index 4fe82d613..7d2b57f9a 100755 --- a/sysdrv/source/kernel/arch/arm/configs/luckfox_rv1106_linux_defconfig +++ b/sysdrv/source/kernel/arch/arm/configs/luckfox_rv1106_linux_defconfig @@ -196,7 +196,9 @@ CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_ROCKCHIP_CIF=m CONFIG_VIDEO_ROCKCHIP_ISP=m CONFIG_VIDEO_RK_IRCUT=y +CONFIG_VIDEO_IMX415=m CONFIG_VIDEO_MIS5001=m +CONFIG_VIDEO_MIA1321=m CONFIG_VIDEO_SC3336=m CONFIG_DRM=y CONFIG_DRM_EDID=y diff --git a/sysdrv/source/kernel/drivers/media/i2c/Kconfig b/sysdrv/source/kernel/drivers/media/i2c/Kconfig index c00b2b78e..9394b5502 100644 --- a/sysdrv/source/kernel/drivers/media/i2c/Kconfig +++ b/sysdrv/source/kernel/drivers/media/i2c/Kconfig @@ -1864,6 +1864,17 @@ config VIDEO_MIS5001 This is a Video4Linux2 sensor driver for the ImageDesign MIS5001 camera. +config VIDEO_MIA1321 + tristate "ImageDesign mia1321 sensor support" + depends on I2C && VIDEO_V4L2 + depends on I2C && VIDEO_V4L2 + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the ImageDesign + MIA1321 camera. + config VIDEO_MT9M001 tristate "mt9m001 support" depends on I2C && VIDEO_V4L2 diff --git a/sysdrv/source/kernel/drivers/media/i2c/Makefile b/sysdrv/source/kernel/drivers/media/i2c/Makefile index b23d8a1e6..79af2c054 100644 --- a/sysdrv/source/kernel/drivers/media/i2c/Makefile +++ b/sysdrv/source/kernel/drivers/media/i2c/Makefile @@ -120,6 +120,7 @@ obj-$(CONFIG_VIDEO_OV13858) += ov13858.o obj-$(CONFIG_VIDEO_MIS2031) += mis2031.o obj-$(CONFIG_VIDEO_MIS4001) += mis4001.o obj-$(CONFIG_VIDEO_MIS5001) += mis5001.o +obj-$(CONFIG_VIDEO_MIA1321) += mia1321.o obj-$(CONFIG_VIDEO_MT9M001) += mt9m001.o obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o obj-$(CONFIG_VIDEO_MT9M111) += mt9m111.o diff --git a/sysdrv/source/kernel/drivers/media/i2c/imx415.c b/sysdrv/source/kernel/drivers/media/i2c/imx415.c index e526518e3..f26e2edf4 100644 --- a/sysdrv/source/kernel/drivers/media/i2c/imx415.c +++ b/sysdrv/source/kernel/drivers/media/i2c/imx415.c @@ -76,6 +76,7 @@ #define IMX415_XVCLK_FREQ_37M 37125000 #define IMX415_XVCLK_FREQ_27M 27000000 +#define IMX415_XVCLK_FREQ_24M 24000000 /* TODO: Get the real chip id from reg */ #define CHIP_ID 0xE0 @@ -680,6 +681,41 @@ static __maybe_unused const struct regval imx415_linear_10bit_3864x2192_891M_reg {REG_NULL, 0x00}, }; +static __maybe_unused const struct regval imx415_linear_10bit_3864x2192_594M_regs[] = { + {0x3020, 0x00}, + {0x3021, 0x00}, + {0x3022, 0x00}, + {0x3024, 0xCA}, + {0x3025, 0x08}, + {0x3028, 0x72}, + {0x3029, 0x06}, + {0x302C, 0x00}, + {0x302D, 0x00}, + {0x3033, 0x07}, + {0x3050, 0x08}, + {0x3051, 0x00}, + {0x3054, 0x19}, + {0x3058, 0x3E}, + {0x3060, 0x25}, + {0x3064, 0x4a}, + {0x30CF, 0x00}, + {0x3118, 0xC0}, + {0x3260, 0x01}, + {0x400C, 0x00}, + {0x4018, 0x67}, + {0x401A, 0x27}, + {0x401C, 0x27}, + {0x401E, 0xB7}, + {0x401F, 0x00}, + {0x4020, 0x2F}, + {0x4022, 0xB7}, + {0x4024, 0x2F}, + {0x4026, 0x47}, + {0x4028, 0x27}, + {0x4074, 0x01}, + {REG_NULL, 0x00}, +}; + static __maybe_unused const struct regval imx415_linear_12bit_1932x1096_594M_regs[] = { {0x3020, 0x01}, {0x3021, 0x01}, @@ -758,6 +794,152 @@ static __maybe_unused const struct regval imx415_hdr2_12bit_1932x1096_891M_regs[ {REG_NULL, 0x00}, }; +/* + * Xclk 37Mhz + * 15fps + * CSI-2_2lane + * AD:10bit Output:10bit + * 891Mbps + * Master Mode + * Time 9.988ms Gain:6dB + * All-pixel + */ +static __maybe_unused const struct regval imx415_linear_10bit_3864x2192_891M_regs_2lane[] = { + {0x3008, 0x5D}, + {0x300A, 0x42}, + {0x3028, 0x98}, + {0x3029, 0x08}, + {0x3031, 0x00}, + {0x3033, 0x05}, + {0x3050, 0x79}, + {0x3051, 0x07}, + {0x3090, 0x14}, + {0x30C1, 0x00}, + {0x3116, 0x23}, + {0x3118, 0xC6}, + {0x311A, 0xE7}, + {0x311E, 0x23}, + {0x32D4, 0x21}, + {0x32EC, 0xA1}, + {0x344C, 0x2B}, + {0x344D, 0x01}, + {0x344E, 0xED}, + {0x344F, 0x01}, + {0x3450, 0xF6}, + {0x3451, 0x02}, + {0x3452, 0x7F}, + {0x3453, 0x03}, + {0x358A, 0x04}, + {0x35A1, 0x02}, + {0x35EC, 0x27}, + {0x35EE, 0x8D}, + {0x35F0, 0x8D}, + {0x35F2, 0x29}, + {0x36BC, 0x0C}, + {0x36CC, 0x53}, + {0x36CD, 0x00}, + {0x36CE, 0x3C}, + {0x36D0, 0x8C}, + {0x36D1, 0x00}, + {0x36D2, 0x71}, + {0x36D4, 0x3C}, + {0x36D6, 0x53}, + {0x36D7, 0x00}, + {0x36D8, 0x71}, + {0x36DA, 0x8C}, + {0x36DB, 0x00}, + {0x3720, 0x00}, + {0x3724, 0x02}, + {0x3726, 0x02}, + {0x3732, 0x02}, + {0x3734, 0x03}, + {0x3736, 0x03}, + {0x3742, 0x03}, + {0x3862, 0xE0}, + {0x38CC, 0x30}, + {0x38CD, 0x2F}, + {0x395C, 0x0C}, + {0x39A4, 0x07}, + {0x39A8, 0x32}, + {0x39AA, 0x32}, + {0x39AC, 0x32}, + {0x39AE, 0x32}, + {0x39B0, 0x32}, + {0x39B2, 0x2F}, + {0x39B4, 0x2D}, + {0x39B6, 0x28}, + {0x39B8, 0x30}, + {0x39BA, 0x30}, + {0x39BC, 0x30}, + {0x39BE, 0x30}, + {0x39C0, 0x30}, + {0x39C2, 0x2E}, + {0x39C4, 0x2B}, + {0x39C6, 0x25}, + {0x3A42, 0xD1}, + {0x3A4C, 0x77}, + {0x3AE0, 0x02}, + {0x3AEC, 0x0C}, + {0x3B00, 0x2E}, + {0x3B06, 0x29}, + {0x3B98, 0x25}, + {0x3B99, 0x21}, + {0x3B9B, 0x13}, + {0x3B9C, 0x13}, + {0x3B9D, 0x13}, + {0x3B9E, 0x13}, + {0x3BA1, 0x00}, + {0x3BA2, 0x06}, + {0x3BA3, 0x0B}, + {0x3BA4, 0x10}, + {0x3BA5, 0x14}, + {0x3BA6, 0x18}, + {0x3BA7, 0x1A}, + {0x3BA8, 0x1A}, + {0x3BA9, 0x1A}, + {0x3BAC, 0xED}, + {0x3BAD, 0x01}, + {0x3BAE, 0xF6}, + {0x3BAF, 0x02}, + {0x3BB0, 0xA2}, + {0x3BB1, 0x03}, + {0x3BB2, 0xE0}, + {0x3BB3, 0x03}, + {0x3BB4, 0xE0}, + {0x3BB5, 0x03}, + {0x3BB6, 0xE0}, + {0x3BB7, 0x03}, + {0x3BB8, 0xE0}, + {0x3BBA, 0xE0}, + {0x3BBC, 0xDA}, + {0x3BBE, 0x88}, + {0x3BC0, 0x44}, + {0x3BC2, 0x7B}, + {0x3BC4, 0xA2}, + {0x3BC8, 0xBD}, + {0x3BCA, 0xBD}, + {0x4001, 0x01}, + {0x4004, 0xC0}, + {0x4005, 0x06}, + {0x400C, 0x00}, + {0x4018, 0x7F}, + {0x401A, 0x37}, + {0x401C, 0x37}, + {0x401E, 0xF7}, + {0x401F, 0x00}, + {0x4020, 0x3F}, + {0x4022, 0x6F}, + {0x4024, 0x3F}, + {0x4026, 0x5F}, + {0x4028, 0x2F}, + {0x4074, 0x01}, + {0x3002, 0x00}, + //{0x3000, 0x00}, + {REG_DELAY, 0x1E},//wait_ms(30) + {REG_NULL, 0x00}, +}; + + /* * Xclk 27Mhz * 15fps @@ -1080,6 +1262,25 @@ static const struct imx415_mode supported_modes[] = { * frame rate = 1 / (Vtt * 1H) = 1 / (VMAX * 1H) * VMAX >= (PIX_VWIDTH / 2) + 46 = height + 46 */ + { + .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10, + .width = 3864, + .height = 2192, + .max_fps = { + .numerator = 10000, + .denominator = 200000, + }, + .exp_def = 0x08ca - 0x08, + .hts_def = 0x044c * IMX415_4LANES * 2, + .vts_def = 0x08ca, + .global_reg_list = imx415_global_10bit_3864x2192_regs, + .reg_list = imx415_linear_10bit_3864x2192_594M_regs, + .hdr_mode = NO_HDR, + .mipi_freq_idx = 1, + .bpp = 10, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + .xvclk = IMX415_XVCLK_FREQ_37M, + }, { .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10, .width = 3864, @@ -1337,6 +1538,26 @@ static const struct imx415_mode supported_modes_2lane[] = { .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, .xvclk = IMX415_XVCLK_FREQ_27M, }, + { + /* 1H period = (1100 clock) = (1100 * 1 / 74.25MHz) */ + .bus_fmt = MEDIA_BUS_FMT_SGBRG10_1X10, + .width = 3864, + .height = 2192, + .max_fps = { + .numerator = 10000, + .denominator = 150000, + }, + .exp_def = 0x08ca - 0x08, + .hts_def = 0x0898 * IMX415_2LANES * 2, + .vts_def = 0x08ca, + .global_reg_list = NULL, + .reg_list = imx415_linear_10bit_3864x2192_891M_regs_2lane, + .hdr_mode = NO_HDR, + .mipi_freq_idx = 1, + .bpp = 10, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + .xvclk = IMX415_XVCLK_FREQ_37M, + }, }; static const s64 link_freq_items[] = { diff --git a/sysdrv/source/kernel/drivers/media/i2c/mia1321.c b/sysdrv/source/kernel/drivers/media/i2c/mia1321.c new file mode 100755 index 000000000..3f84a3b0e --- /dev/null +++ b/sysdrv/source/kernel/drivers/media/i2c/mia1321.c @@ -0,0 +1,1844 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * mia1321 driver + * + * Copyright (C) 2023 Rockchip Electronics Co., Ltd. + * + * V0.0X01.0X01 first version + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../platform/rockchip/isp/rkisp_tb_helper.h" + +#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01) + +#define MIA1321_LANES 2 +#define MIA1321_BITS_PER_SAMPLE 12 +#define MIA1321_LINK_FREQ_37125 576000000 //37.125mbp + +#define PIXEL_RATE_WITH_315M_10BIT (MIA1321_LINK_FREQ_37125 / MIA1321_BITS_PER_SAMPLE * 2 * \ + MIA1321_LANES) +#define MIA1321_XVCLK_FREQ 26000000 + +#define CHIP_ID 0x0400 +#define MIA1321_REG_CHIP_ID 0x0011 + +#define MIA1321_REG_CTRL_MODE 0x0126 +#define MIA1321_MODE_SW_STANDBY BIT(0) +#define MIA1321_MODE_STREAMING 0x0 + +#define MIA1321_REG_EXPOSURE_H 0x00cf +#define MIA1321_REG_EXPOSURE_M 0x00ce +#define MIA1321_REG_EXPOSURE_L 0x00cd +#define MIA1321_REG_EXPOSURE_STEP 50 //depend on ref clk and vts +#define MIA1321_EXPOSURE_MIN 1 +#define MIA1321_EXPOSURE_STEP 1 +#define MIA1321_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0xFF) +#define MIA1321_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF) +#define MIA1321_FETCH_EXP_L(VAL) ((VAL) & 0xFF) + +#define MIA1321_REG_DIG_GAIN_EN 0 +#define MIA1321_REG_DIG_GAIN_ADDRRE_EN 0x0120 // 1 function able; 0 function disable +#define MIA1321_REG_DIG_GAIN_COARSE 0x0122 //[5:0] setp = 1 +#define MIA1321_REG_DIG_GAIN_FINE_H 0x0124 //[9:8] setp = 1/1024 +#define MIA1321_REG_DIG_GAIN_FINE_L 0x0123 //[7:0] setp = 1/1024 + +#define MIA1321_REG_ANA_GAIN_H 0x001b +#define MIA1321_REG_ANA_GAIN_M 0x0019 +#define MIA1321_REG_ANA_GAIN_L 0x0018 + +#define MIA1321_ONCE_GAIN_STEP 0x5dc +#define MIA1321_GAIN_MIN MIA1321_ONCE_GAIN_STEP +#define MIA1321_AGAIN_MAX (MIA1321_ONCE_GAIN_STEP * 32) /* just again */ +#define MIA1321_GAIN_MAX (MIA1321_AGAIN_MAX * 1) +#define MIA1321_GAIN_STEP 1 +#define MIA1321_GAIN_DEFAULT MIA1321_ONCE_GAIN_STEP +#define MIA1321_FETCH_DIG_COARSE_GAIN_H(VAL) (((VAL) >> 8) & 0x05) +#define MIA1321_FETCH_DIG_FINE_GAIN_H(VAL) ((VAL) & 0xFF) +#define MIA1321_FETCH_DIG_FINE_GAIN_L(VAL) ((VAL) & 0xFF) + +#define MIA1321_VTS_MAX 0xffff +//#define MIA1321_REG_VTS_H 0x1027 +//#define MIA1321_REG_VTS_L 0x1026 +//#define MIA1321_REG_VTS_VALUE 1080 + +#define MIA1321_MIRROR_REG 0x009a +#define MIA1321_FLIP_REG 0x0099 +#define MIRROR_BIT_MASK BIT(0) +#define FLIP_BIT_MASK BIT(1) +#define MIA1321_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xfe) +#define MIA1321_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x10 : VAL & 0xfd) + +//#define MIA1321_REG_TEST_PATTERN 0x3500 +//#define MIA1321_TEST_PATTERN_BIT_MASK BIT(0) + +#define REG_DELAY 0xFFFE +#define REG_NULL 0xFFFF + +#define MIA1321_REG_VALUE_08BIT 1 +#define MIA1321_REG_VALUE_16BIT 2 +#define MIA1321_REG_VALUE_24BIT 3 + +#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default" +#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep" +#define MIA1321_NAME "mia1321" + +static const char *const mia1321_supply_names[] = { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + +#define MIA1321_NUM_SUPPLIES ARRAY_SIZE(mia1321_supply_names) + +struct regval { + u16 addr; + u8 val; +}; + +struct mia1321_mode { + u32 bus_fmt; + u32 width; + u32 height; + struct v4l2_fract max_fps; + u32 hts_def; + u32 vts_def; + u32 exp_def; + const struct regval *reg_list; + u32 hdr_mode; + u32 vc[PAD_MAX]; +}; + +struct mia1321 { + struct i2c_client *client; + struct clk *xvclk; + struct gpio_desc *reset_gpio; + struct gpio_desc *pwdn_gpio; + struct regulator_bulk_data supplies[MIA1321_NUM_SUPPLIES]; + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; + + struct v4l2_subdev subdev; + struct media_pad pad; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *anal_gain; + struct v4l2_ctrl *digi_gain; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *test_pattern; + struct mutex mutex; + bool streaming; + bool power_on; + const struct mia1321_mode *cur_mode; + struct v4l2_fract cur_fps; + u32 module_index; + const char *module_facing; + const char *module_name; + const char *len_name; + u32 cur_vts; + bool is_thunderboot; + bool is_first_streamoff; + bool is_mirror; + bool is_flip; +}; + +#define to_mia1321(sd) container_of(sd, struct mia1321, subdev) + +/* + * Xclk 24Mhz + */ +static const struct regval mia1321_global_regs[] = { + {REG_NULL, 0x00}, +}; + +static const struct regval mia1321_linear_60_1280x1080_regs[] = { + //input:26M + //size:1280*1080 + //fps:60 + //mipi 2lane + + {0x011d, 0x00}, //10BIT + + {0x011f, 0x00}, + + {0x012e, 0x02}, + {0x012b, 0x01}, + + {0x00bd, 0x00}, + {0x00bc, 0x01}, + + {0x00bf, 0x00}, + {0x00c0, 0x00}, + + {0x00cd, 0x01}, + {0x00ce, 0x01}, + {0x00cf, 0x00}, + {0x00e1, 0x00}, + {0x011c, 0x00}, + {0x0120, 0x00}, + {0x0125, 0x00}, + {0x003c, 0x01}, + {0x003d, 0x03}, + {0x1201, 0xf0}, + {0x1051, 0x1e}, + {0x1202, 0x70}, + {0x1203, 0x10}, + {0x1070, 0x02}, + {0x1205, 0x00}, + {0x1208, 0x01}, + {0x1000, 0x16}, + {0x1024, 0x00}, + {0x1025, 0x05}, + {0x1026, 0x38}, + {0x1027, 0x04}, + {0x1020, 0x2a}, + {0x1042, 0x03}, + {0x0010, 0x05}, + {0x0012, 0x01}, + {0x0043, 0x03}, + {0x003f, 0x3f}, + {0x0041, 0xff}, //0x3f default: mipi single strength adjust + + {0x009a, 0x01}, //MIRROR + {0x0099, 0x01}, //FLIP + + {0x00ca, 0x01}, + {0x00e1, 0x00}, + {0x00e2, 0x00}, + {0x0030, 0xc0}, + {0x012c, 0x01}, + + //60fps + {0x004a, 0x01}, //PLL_OUTDIV + {0x004b, 0x90}, //PLL_FBDIV + {0x004c, 0x03}, //PLL_DIV_ADC + {0x004e, 0x01}, //PLL_DIV_BITCLK + {0x0051, 0x03}, //PLL_DIV_PCLK + {0x0053, 0x03}, //PLL_DIV_CPCLK + + {0x00d0, 0x9a}, //fot_num 666 + {0x00d1, 0x02}, //fot_num 666 + {0x00df, 0x42}, //fot_line + {0x01c9, 0x9a}, //col_n 666(HS) + {0x01ca, 0x02}, //col_n 666(HS) + {0x0043, 0x01}, + {0x02fd, 0x58}, + {0x02fe, 0x42}, + {0x031f, 0xb0}, + {0x0320, 0x04}, + {0x0305, 0x08}, + {0x0306, 0x87}, + {0x0307, 0xfc}, + {0x0308, 0x08}, + {0x0317, 0x80}, + {0x0318, 0x0c}, + {0x030f, 0xfa}, + {0x0310, 0x0f}, + {0x02ff, 0xfa}, + {0x0300, 0x8f}, + {0x0309, 0xfa}, + {0x030a, 0x8f}, + {0x00ce, 0x03}, + {0x1000, 0x06}, + {0x1018, 0x01}, + {0x1018, 0x00}, + {0x012a, 0x01}, + {0x012a, 0x00}, + {0x00ce, 0x00}, + {0x00cd, 0x01}, + + {0x012a, 0x01}, + {0x012a, 0x00}, + {REG_NULL, 0x00}, +}; +static const struct regval mia1321_linear_120_1280x1080_regs[] = { + //input:26M + //size:1280*1080 + //fps:117 + //mipi 2lane + + {0x011d, 0x00}, //10BIT + + {0x011f, 0x00}, + + {0x012e, 0x02}, + {0x012b, 0x01}, + + {0x00bd, 0x00}, + {0x00bc, 0x01}, + + {0x00bf, 0x00}, + {0x00c0, 0x00}, + + {0x00cd, 0x01}, + {0x00ce, 0x01}, + {0x00cf, 0x00}, + {0x00e1, 0x00}, + {0x011c, 0x00}, + {0x0120, 0x00}, + {0x0125, 0x00}, + {0x003c, 0x01}, + {0x003d, 0x03}, + {0x1201, 0xf0}, + {0x1051, 0x1e}, + {0x1202, 0x70}, + {0x1203, 0x10}, + {0x1070, 0x02}, + {0x1205, 0x00}, + {0x1208, 0x01}, + {0x1000, 0x16}, + {0x1024, 0x00}, + {0x1025, 0x05}, + {0x1026, 0x38}, + {0x1027, 0x04}, + {0x1020, 0x2a}, + {0x1042, 0x03}, + {0x0010, 0x05}, + {0x0012, 0x01}, + {0x0043, 0x03}, + {0x003f, 0x3f}, + {0x0041, 0xff}, //0x3f default: mipi single strength adjust + {0x00ca, 0x01}, + {0x00e1, 0x00}, + {0x00e2, 0x00}, + {0x0030, 0xc0}, + {0x012c, 0x01}, + + //117fps + {0x004a, 0x01},//PLL_OUTDIV + {0x004b, 0xd8},//PLL_FBDIV 117fps + //{0x004b, 0xC0},//PLL_FBDIV 100fps + {0x004c, 0x02},//PLL_DIV_ADC + {0x004e, 0x01},//PLL_DIV_BITCLK + {0x0051, 0x02},//PLL_DIV_PCLK + {0x0053, 0x02},//PLL_DIV_CPCLK + + {0x00d0, 0x9a}, //fot_num 666 + {0x00d1, 0x02}, //fot_num 666 + {0x00df, 0x42}, //fot_line + {0x01c9, 0x9a}, //col_n 666(HS) + {0x01ca, 0x02}, //col_n 666(HS) + {0x0043, 0x01}, + {0x02fd, 0x58}, + {0x02fe, 0x42}, + {0x031f, 0xb0}, + {0x0320, 0x04}, + {0x0305, 0x08}, + {0x0306, 0x87}, + {0x0307, 0xfc}, + {0x0308, 0x08}, + {0x0317, 0x80}, + {0x0318, 0x0c}, + {0x030f, 0xfa}, + {0x0310, 0x0f}, + {0x02ff, 0xfa}, + {0x0300, 0x8f}, + {0x0309, 0xfa}, + {0x030a, 0x8f}, + {0x00ce, 0x03}, + {0x1000, 0x06}, + {0x1018, 0x01}, + {0x1018, 0x00}, + {0x012a, 0x01}, + {0x012a, 0x00}, + {0x00ce, 0x00}, + {0x00cd, 0x01}, + + {0x012a, 0x01}, + {0x012a, 0x00}, + {REG_NULL, 0x00}, +}; +static const struct regval mia1321_linear_10_1280x720_regs[] = { + //input:24M + //size:1280*1080 + //fps:30 + //pclk:24M + //mipi 2lane + //hts:666*4 + //vts:1080+48+6+66 + + {0x011d, 0x01}, + {0x011f, 0x00}, + {0x012e, 0x02}, + {0x012b, 0x01}, + {0x00bd, 0x00}, + {0x00bc, 0x01}, + {0x00bf, 0x05}, + {0x00c0, 0x00}, + {0x00cd, 0x01}, + {0x00ce, 0x01}, + {0x00cf, 0x00}, + {0x00e1, 0x00}, + {0x011c, 0x00}, + {0x0120, 0x00}, + {0x0125, 0x00}, + {0x003c, 0x01}, + {0x003d, 0x03}, + {0x1201, 0xf0}, + {0x1051, 0x1e}, + {0x1202, 0x70}, + {0x1203, 0x10}, + {0x1070, 0x02}, + {0x1205, 0x00}, + {0x1208, 0x01}, + {0x1000, 0x16}, + {0x1024, 0x00}, + {0x1025, 0x05}, + {0x1026, 0x38}, + {0x1027, 0x04}, + {0x1020, 0x2a}, + {0x1042, 0x03}, + {0x0010, 0x05}, + {0x0012, 0x01}, + {0x0043, 0x03}, + {0x003f, 0x3f}, + {0x0041, 0xff}, //0x3f default: mipi single strength adjust + {0x00ca, 0x01}, + {0x00e1, 0x00}, + {0x00e2, 0x00}, + {0x0030, 0xc0}, + {0x012c, 0x01}, + {0x004a, 0x01}, + {0x004b, 0x60}, + {0x00d0, 0x9a}, //fot_num 666 + {0x00d1, 0x02}, //fot_num 666 + {0x00df, 0x42}, //fot_line + {0x01c9, 0x9a}, //col_n 666(HS) + {0x01ca, 0x02}, //col_n 666(HS) + {0x0043, 0x01}, + {0x02fd, 0x58}, + {0x02fe, 0x42}, + {0x031f, 0xb0}, + {0x0320, 0x04}, + {0x0305, 0x08}, + {0x0306, 0x87}, + {0x0307, 0xfc}, + {0x0308, 0x08}, + {0x0317, 0x80}, + {0x0318, 0x0c}, + {0x030f, 0xfa}, + {0x0310, 0x0f}, + {0x02ff, 0xfa}, + {0x0300, 0x8f}, + {0x0309, 0xfa}, + {0x030a, 0x8f}, + {0x00ce, 0x03}, + {0x1000, 0x06}, + {0x1018, 0x01}, + {0x1018, 0x00}, + {0x012a, 0x01}, + {0x012a, 0x00}, + {0x00ce, 0x00}, + {0x00cd, 0x01}, + + {0x012a, 0x01}, + {0x012a, 0x00}, + {REG_NULL, 0x00}, +}; + + +static const struct mia1321_mode supported_modes[] = { + { + .width = 1280, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 600000, + }, + .exp_def = 0x01f4, + .hts_def = 0x0a68, + .vts_def = 0x04b0, + .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10, + .reg_list = mia1321_linear_60_1280x1080_regs, + .hdr_mode = NO_HDR, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + }, + { + .width = 1280, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 1170000, + }, + .exp_def = 0x01f4, + .hts_def = 0x0a68, + .vts_def = 0x04b0, + .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10, + .reg_list = mia1321_linear_120_1280x1080_regs, + .hdr_mode = NO_HDR, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + }, + { + .width = 1280, + .height = 1080, + .max_fps = { + .numerator = 10000, + .denominator = 300000, + }, + .exp_def = 0x0052, + .hts_def = 0x0a68, + .vts_def = 0x04b0, + .bus_fmt = MEDIA_BUS_FMT_SGRBG12_1X12, + .reg_list = mia1321_linear_10_1280x720_regs, + .hdr_mode = NO_HDR, + .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0, + } +}; + +static const s64 link_freq_menu_items[] = { + MIA1321_LINK_FREQ_37125 +}; + +static const char *const mia1321_test_pattern_menu[] = { + "Disabled", + "Vertical Color Bar Type 1", + "Vertical Color Bar Type 2", + "Vertical Color Bar Type 3", + "Vertical Color Bar Type 4" +}; + +/* Write registers up to 4 at a time */ +static int mia1321_write_reg(struct i2c_client *client, u16 reg, + u32 len, u32 val) +{ + u32 buf_i, val_i; + u8 buf[6]; + u8 *val_p; + __be32 val_be; + + if (len > 4) + return -EINVAL; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + + val_be = cpu_to_be32(val); + val_p = (u8 *)&val_be; + buf_i = 2; + val_i = 4 - len; + + while (val_i < 4) + buf[buf_i++] = val_p[val_i++]; + + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +static int mia1321_write_array(struct i2c_client *client, + const struct regval *regs) +{ + u32 i; + int ret = 0; + + for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) { + if (regs[i].addr == REG_DELAY) + mdelay(regs[i].val); + else + ret = mia1321_write_reg(client, regs[i].addr, + MIA1321_REG_VALUE_08BIT, regs[i].val); + } + + return ret; +} + +/* Read registers up to 4 at a time */ +static int mia1321_read_reg(struct i2c_client *client, u16 reg, unsigned int len, + u32 *val) +{ + struct i2c_msg msgs[2]; + u8 *data_be_p; + __be32 data_be = 0; + __be16 reg_addr_be = cpu_to_be16(reg); + int ret; + + if (len > 4 || !len) + return -EINVAL; + + data_be_p = (u8 *)&data_be; + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = 2; + msgs[0].buf = (u8 *)®_addr_be; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = &data_be_p[4 - len]; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = be32_to_cpu(data_be); + + return 0; +} + +static void mia1321_set_orientation_reg(struct mia1321 *mia1321, u32 en_flip_mir) +{ + switch (en_flip_mir) { + case 0: + mia1321->is_flip = false; + mia1321->is_mirror = false; + mia1321_write_reg(mia1321->client, MIA1321_FLIP_REG, + MIA1321_REG_VALUE_08BIT, 0x00); + mia1321_write_reg(mia1321->client, MIA1321_MIRROR_REG, + MIA1321_REG_VALUE_08BIT, 0x00); + break; + case 1: + mia1321->is_flip = false; + mia1321->is_mirror = true; + mia1321_write_reg(mia1321->client, MIA1321_FLIP_REG, + MIA1321_REG_VALUE_08BIT, 0x00); + mia1321_write_reg(mia1321->client, MIA1321_MIRROR_REG, + MIA1321_REG_VALUE_08BIT, 0x01); + break; + case 2: + mia1321->is_flip = true; + mia1321->is_mirror = false; + mia1321_write_reg(mia1321->client, MIA1321_FLIP_REG, + MIA1321_REG_VALUE_08BIT, 0x01); + mia1321_write_reg(mia1321->client, MIA1321_MIRROR_REG, + MIA1321_REG_VALUE_08BIT, 0x00); + break; + case 3: + mia1321->is_flip = true; + mia1321->is_mirror = true; + mia1321_write_reg(mia1321->client, MIA1321_FLIP_REG, + MIA1321_REG_VALUE_08BIT, 0x01); + mia1321_write_reg(mia1321->client, MIA1321_MIRROR_REG, + MIA1321_REG_VALUE_08BIT, 0x01); + break; + default: + mia1321->is_flip = false; + mia1321->is_mirror = false; + mia1321_write_reg(mia1321->client, MIA1321_FLIP_REG, + MIA1321_REG_VALUE_08BIT, 0x00); + mia1321_write_reg(mia1321->client, MIA1321_MIRROR_REG, + MIA1321_REG_VALUE_08BIT, 0x00); + break; + } +} + +struct s_again { + // total_gain = 2^ramp_gainctrl_1[8:7]*(1+ramp_gainctrl_1[6:0]/16) + u32 again; + u32 reg_0018; // ramp_gainctrl_1[7:0] [0] + u32 reg_0019; // ramp_gainctrl_1[8] [0] + u32 reg_001b; +}; + +static const struct s_again mia1321_again[] = { + //again, reg_0x18, reg_0x19, reg_0x1b + {800, 0x0, 0x0, 0x1f}, + {1000, 0x4, 0x0, 0x1f}, + {1250, 0x9, 0x0, 0x1f}, + {1500, 0xE, 0x0, 0x1f}, + {1750, 0x13, 0x0, 0x2b}, + {2200, 0x1C, 0x0, 0x2b}, + {2450, 0x21, 0x0, 0x2b}, + {2700, 0x26, 0x0, 0x2b}, + {2950, 0x2B, 0x0, 0x2b}, + {3400, 0x34, 0x0, 0x30}, + {3650, 0x39, 0x0, 0x30}, + {3900, 0x3E, 0x0, 0x30}, + {4150, 0x43, 0x0, 0x30}, + {4600, 0x4C, 0x0, 0x30}, + {4850, 0x51, 0x0, 0x30}, + {5100, 0x56, 0x0, 0x30}, + {5350, 0x5B, 0x0, 0x30}, + {5800, 0x64, 0x0, 0x30}, + {6050, 0x69, 0x0, 0x30}, + {6300, 0x6E, 0x0, 0x30}, + {6550, 0x73, 0x0, 0x32}, + {7000, 0x7c, 0x0, 0x32}, + {7800, 0xbe, 0x0, 0x32}, + {8800, 0xc8, 0x0, 0x32}, + {9800, 0xd2, 0x0, 0x32}, + {10800, 0xdc, 0x0, 0x32}, + {12600, 0xee, 0x0, 0x32}, + {13600, 0xf8, 0x0, 0x32}, + {14600, 0x39, 0x1, 0x32}, + {15600, 0x3E, 0x1, 0x32}, + {17400, 0x47, 0x1, 0x32}, + {18400, 0x4C, 0x1, 0x32}, + {19400, 0x51, 0x1, 0x32}, + {20400, 0x56, 0x1, 0x32}, + {22200, 0x5F, 0x1, 0x32}, + {23200, 0x64, 0x1, 0x32}, + {24200, 0x69, 0x1, 0x32}, + {25200, 0x6E, 0x1, 0x32}, + {25600, 0x70, 0x1, 0x32},// MIA1321_GAIN_MAX +}; + +static int mia1321_set_gain_reg(struct mia1321 *mia1321, u32 gain) +{ + + int ret = 0, i = 0;//, dgain; + u8 gain_0x0018 = 0x00; + u8 gain_0x0019 = 0x00; + u8 gain_0x001b = 0x1f; + + //struct device *dev = &mia1321->client->dev; + dev_info(&(mia1321->client->dev), "-----gain ------------ %d\n", gain); + if (gain <= MIA1321_GAIN_MIN) + gain = MIA1321_GAIN_MIN; + + if (gain > MIA1321_GAIN_MAX - 1) + gain = MIA1321_GAIN_MAX - 1; + + while (i < ARRAY_SIZE(mia1321_again)) { + if (gain <= mia1321_again[i].again) { + gain_0x001b = mia1321_again[i].reg_001b; + gain_0x0019 = mia1321_again[i].reg_0019; + gain_0x0018 = mia1321_again[i].reg_0018; + break; + } + if (gain >= MIA1321_GAIN_MAX - 1) { + gain_0x001b = 0x32; + gain_0x0019 = 1; + gain_0x0018 = 0x70; + break; + } + i++; + } + + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_ANA_GAIN_H, + MIA1321_REG_VALUE_08BIT, + gain_0x001b); + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_ANA_GAIN_M, + MIA1321_REG_VALUE_08BIT, + gain_0x0019); + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_ANA_GAIN_L, + MIA1321_REG_VALUE_08BIT, + gain_0x0018); + +#if MIA1321_REG_DIG_GAIN_EN == 1 + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_DIG_GAIN_ADDRRE_EN, + MIA1321_REG_VALUE_08BIT, + MIA1321_REG_DIG_GAIN_EN); + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_DIG_GAIN_COARSE, + MIA1321_REG_VALUE_08BIT, + MIA1321_FETCH_DIG_FINE_GAIN_H(dgain)); + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_DIG_GAIN_FINE_H, + MIA1321_REG_VALUE_08BIT, + MIA1321_FETCH_DIG_FINE_GAIN_H(dgain)); + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_DIG_GAIN_FINE_L, + MIA1321_REG_VALUE_08BIT, + MIA1321_FETCH_DIG_FINE_GAIN_L(dgain)); +#endif + + return ret; +} + +static int mia1321_get_reso_dist(const struct mia1321_mode *mode, + struct v4l2_mbus_framefmt *framefmt) +{ + return abs(mode->width - framefmt->width) + + abs(mode->height - framefmt->height); +} + +static const struct mia1321_mode * +mia1321_find_best_fit(struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *framefmt = &fmt->format; + int dist; + int cur_best_fit = 0; + int cur_best_fit_dist = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + dist = mia1321_get_reso_dist(&supported_modes[i], framefmt); + if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) { + cur_best_fit_dist = dist; + cur_best_fit = i; + } + } + + return &supported_modes[cur_best_fit]; +} + +static int mia1321_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + const struct mia1321_mode *mode; + s64 h_blank, vblank_def; + + mutex_lock(&mia1321->mutex); + + mode = mia1321_find_best_fit(fmt); + fmt->format.code = mode->bus_fmt; + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.field = V4L2_FIELD_NONE; + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format; +#else + mutex_unlock(&mia1321->mutex); + return -ENOTTY; +#endif + } else { + mia1321->cur_mode = mode; + h_blank = mode->hts_def - mode->width; + __v4l2_ctrl_modify_range(mia1321->hblank, h_blank, + h_blank, 1, h_blank); + vblank_def = mode->vts_def - mode->height; + __v4l2_ctrl_modify_range(mia1321->vblank, vblank_def, + MIA1321_VTS_MAX - mode->height, + 1, vblank_def); + mia1321->cur_fps = mode->max_fps; + } + + mutex_unlock(&mia1321->mutex); + + return 0; +} + +static int mia1321_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + const struct mia1321_mode *mode = mia1321->cur_mode; + + mutex_lock(&mia1321->mutex); + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad); +#else + mutex_unlock(&mia1321->mutex); + return -ENOTTY; +#endif + } else { + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->bus_fmt; + fmt->format.field = V4L2_FIELD_NONE; + /* format info: width/height/data type/virctual channel */ + if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR) + fmt->reserved[0] = mode->vc[fmt->pad]; + else + fmt->reserved[0] = mode->vc[PAD0]; + } + mutex_unlock(&mia1321->mutex); + + return 0; +} + +static int mia1321_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + + if (code->index != 0) + return -EINVAL; + code->code = mia1321->cur_mode->bus_fmt; + + return 0; +} + +static int mia1321_enum_frame_sizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code != supported_modes[0].bus_fmt) + return -EINVAL; + + fse->min_width = supported_modes[fse->index].width; + fse->max_width = supported_modes[fse->index].width; + fse->max_height = supported_modes[fse->index].height; + fse->min_height = supported_modes[fse->index].height; + + return 0; +} + +static int mia1321_enable_test_pattern(struct mia1321 *mia1321, u32 pattern) +{ + //u32 val = 0; + int ret = 0; + + /* + ret = mia1321_read_reg(mia1321->client, MIA1321_REG_TEST_PATTERN, + MIA1321_REG_VALUE_08BIT, &val); + if (pattern) + val |= MIA1321_TEST_PATTERN_BIT_MASK; + else + val &= ~MIA1321_TEST_PATTERN_BIT_MASK; + + ret |= mia1321_write_reg(mia1321->client, MIA1321_REG_TEST_PATTERN, + MIA1321_REG_VALUE_08BIT, val); + */ + return ret; +} + +static int mia1321_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *fi) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + const struct mia1321_mode *mode = mia1321->cur_mode; + + if (mia1321->streaming) + fi->interval = mia1321->cur_fps; + else + fi->interval = mode->max_fps; + + return 0; +} + +static int mia1321_g_mbus_config(struct v4l2_subdev *sd, + unsigned int pad_id, + struct v4l2_mbus_config *config) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + const struct mia1321_mode *mode = mia1321->cur_mode; + u32 val = 1 << (MIA1321_LANES - 1) | + V4L2_MBUS_CSI2_CHANNEL_0 | + V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; + + if (mode->hdr_mode != NO_HDR) + val |= V4L2_MBUS_CSI2_CHANNEL_1; + if (mode->hdr_mode == HDR_X3) + val |= V4L2_MBUS_CSI2_CHANNEL_2; + + config->type = V4L2_MBUS_CSI2_DPHY; + config->flags = val; + + return 0; +} + +static void mia1321_get_module_inf(struct mia1321 *mia1321, + struct rkmodule_inf *inf) +{ + memset(inf, 0, sizeof(*inf)); + strscpy(inf->base.sensor, MIA1321_NAME, sizeof(inf->base.sensor)); + strscpy(inf->base.module, mia1321->module_name, + sizeof(inf->base.module)); + strscpy(inf->base.lens, mia1321->len_name, sizeof(inf->base.lens)); +} + +static long mia1321_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + struct rkmodule_hdr_cfg *hdr; + u32 i, h, w; + long ret = 0; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + mia1321_get_module_inf(mia1321, (struct rkmodule_inf *)arg); + break; + case RKMODULE_GET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + hdr->esp.mode = HDR_NORMAL_VC; + hdr->hdr_mode = mia1321->cur_mode->hdr_mode; + break; + case RKMODULE_SET_HDR_CFG: + hdr = (struct rkmodule_hdr_cfg *)arg; + w = mia1321->cur_mode->width; + h = mia1321->cur_mode->height; + for (i = 0; i < ARRAY_SIZE(supported_modes); i++) { + if (w == supported_modes[i].width && + h == supported_modes[i].height && + supported_modes[i].hdr_mode == hdr->hdr_mode) { + mia1321->cur_mode = &supported_modes[i]; + break; + } + } + if (i == ARRAY_SIZE(supported_modes)) { + dev_err(&mia1321->client->dev, + "not find hdr mode:%d %dx%d config\n", + hdr->hdr_mode, w, h); + ret = -EINVAL; + } else { + w = mia1321->cur_mode->hts_def - mia1321->cur_mode->width; + h = mia1321->cur_mode->vts_def - mia1321->cur_mode->height; + __v4l2_ctrl_modify_range(mia1321->hblank, w, w, 1, w); + __v4l2_ctrl_modify_range(mia1321->vblank, h, + MIA1321_VTS_MAX - mia1321->cur_mode->height, 1, h); + } + break; + case PREISP_CMD_SET_HDRAE_EXP: + break; + case RKMODULE_SET_QUICK_STREAM: + + stream = *((u32 *)arg); + + if (stream) + ret = mia1321_write_reg(mia1321->client, MIA1321_REG_CTRL_MODE, + MIA1321_REG_VALUE_08BIT, MIA1321_MODE_STREAMING); + else + ret = mia1321_write_reg(mia1321->client, MIA1321_REG_CTRL_MODE, + MIA1321_REG_VALUE_08BIT, MIA1321_MODE_SW_STANDBY); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long mia1321_compat_ioctl32(struct v4l2_subdev *sd, + unsigned int cmd, unsigned long arg) +{ + void __user *up = compat_ptr(arg); + struct rkmodule_inf *inf; + struct rkmodule_hdr_cfg *hdr; + struct preisp_hdrae_exp_s *hdrae; + long ret; + u32 stream = 0; + + switch (cmd) { + case RKMODULE_GET_MODULE_INFO: + inf = kzalloc(sizeof(*inf), GFP_KERNEL); + if (!inf) { + ret = -ENOMEM; + return ret; + } + + ret = mia1321_ioctl(sd, cmd, inf); + if (!ret) { + if (copy_to_user(up, inf, sizeof(*inf))) + ret = -EFAULT; + } + kfree(inf); + break; + case RKMODULE_GET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = mia1321_ioctl(sd, cmd, hdr); + if (!ret) { + if (copy_to_user(up, hdr, sizeof(*hdr))) + ret = -EFAULT; + } + kfree(hdr); + break; + case RKMODULE_SET_HDR_CFG: + hdr = kzalloc(sizeof(*hdr), GFP_KERNEL); + if (!hdr) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdr, up, sizeof(*hdr)); + if (!ret) + ret = mia1321_ioctl(sd, cmd, hdr); + else + ret = -EFAULT; + kfree(hdr); + break; + case PREISP_CMD_SET_HDRAE_EXP: + hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL); + if (!hdrae) { + ret = -ENOMEM; + return ret; + } + + ret = copy_from_user(hdrae, up, sizeof(*hdrae)); + if (!ret) + ret = mia1321_ioctl(sd, cmd, hdrae); + else + ret = -EFAULT; + kfree(hdrae); + break; + case RKMODULE_SET_QUICK_STREAM: + ret = copy_from_user(&stream, up, sizeof(u32)); + if (!ret) + ret = mia1321_ioctl(sd, cmd, &stream); + else + ret = -EFAULT; + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} +#endif + +static int __mia1321_start_stream(struct mia1321 *mia1321) +{ + int ret; + + if (!mia1321->is_thunderboot) { + ret = mia1321_write_array(mia1321->client, mia1321->cur_mode->reg_list); + if (ret) + return ret; + + /* In case these controls are set before streaming */ + ret = __v4l2_ctrl_handler_setup(&mia1321->ctrl_handler); + + if (ret) + return ret; + } + + ret = mia1321_write_reg(mia1321->client, MIA1321_REG_CTRL_MODE, + MIA1321_REG_VALUE_08BIT, MIA1321_MODE_STREAMING); + + mia1321_write_reg(mia1321->client, MIA1321_FLIP_REG, MIA1321_REG_VALUE_08BIT, 0x01); + mia1321_write_reg(mia1321->client, MIA1321_MIRROR_REG, MIA1321_REG_VALUE_08BIT, 0x01); + + return ret; +} + +static int __mia1321_stop_stream(struct mia1321 *mia1321) +{ + if (mia1321->is_thunderboot) { + mia1321->is_first_streamoff = true; + pm_runtime_put(&mia1321->client->dev); + } + return mia1321_write_reg(mia1321->client, MIA1321_REG_CTRL_MODE, + MIA1321_REG_VALUE_08BIT, MIA1321_MODE_SW_STANDBY); +} + +static int __mia1321_power_on(struct mia1321 *mia1321); +static int mia1321_s_stream(struct v4l2_subdev *sd, int on) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + struct i2c_client *client = mia1321->client; + int ret = 0; + + mutex_lock(&mia1321->mutex); + on = !!on; + if (on == mia1321->streaming) + goto unlock_and_return; + + if (on) { + if (mia1321->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) { + mia1321->is_thunderboot = false; + __mia1321_power_on(mia1321); + } + + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + ret = __mia1321_start_stream(mia1321); + if (ret) { + v4l2_err(sd, "start stream failed while write regs\n"); + pm_runtime_put(&client->dev); + goto unlock_and_return; + } + } else { + __mia1321_stop_stream(mia1321); + pm_runtime_put(&client->dev); + } + + mia1321->streaming = on; + +unlock_and_return: + mutex_unlock(&mia1321->mutex); + + return ret; +} + +static int mia1321_s_power(struct v4l2_subdev *sd, int on) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + struct i2c_client *client = mia1321->client; + int ret = 0; + + mutex_lock(&mia1321->mutex); + + /* If the power state is not modified - no work to do. */ + if (mia1321->power_on == !!on) + goto unlock_and_return; + + if (on) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) { + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + + if (!mia1321->is_thunderboot) { + ret = mia1321_write_array(mia1321->client, mia1321_global_regs); + if (ret) { + v4l2_err(sd, "could not set init registers\n"); + pm_runtime_put_noidle(&client->dev); + goto unlock_and_return; + } + } + + mia1321->power_on = true; + } else { + pm_runtime_put(&client->dev); + mia1321->power_on = false; + } + +unlock_and_return: + mutex_unlock(&mia1321->mutex); + + return ret; +} + +/* Calculate the delay in us by clock rate and clock cycles */ +static inline u32 mia1321_cal_delay(u32 cycles) +{ + return DIV_ROUND_UP(cycles, MIA1321_XVCLK_FREQ / 1000 / 1000); +} + +static int __mia1321_power_on(struct mia1321 *mia1321) +{ + int ret; + u32 delay_us; + struct device *dev = &mia1321->client->dev; + + if (!IS_ERR_OR_NULL(mia1321->pins_default)) { + ret = pinctrl_select_state(mia1321->pinctrl, + mia1321->pins_default); + if (ret < 0) + dev_err(dev, "could not set pins\n"); + } + ret = clk_set_rate(mia1321->xvclk, MIA1321_XVCLK_FREQ); + if (ret < 0) + dev_warn(dev, "Failed to set xvclk rate (24MHz)\n"); + if (clk_get_rate(mia1321->xvclk) != MIA1321_XVCLK_FREQ) + dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n"); + ret = clk_prepare_enable(mia1321->xvclk); + if (ret < 0) { + dev_err(dev, "Failed to enable xvclk\n"); + return ret; + } + if (mia1321->is_thunderboot) + return 0; + + if (!IS_ERR(mia1321->reset_gpio)) + gpiod_set_value_cansleep(mia1321->reset_gpio, 0); + + ret = regulator_bulk_enable(MIA1321_NUM_SUPPLIES, mia1321->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators\n"); + goto disable_clk; + } + + if (!IS_ERR(mia1321->reset_gpio)) + gpiod_set_value_cansleep(mia1321->reset_gpio, 1); + + usleep_range(500, 1000); + if (!IS_ERR(mia1321->pwdn_gpio)) + gpiod_set_value_cansleep(mia1321->pwdn_gpio, 1); + + if (!IS_ERR(mia1321->reset_gpio)) + usleep_range(6000, 8000); + else + usleep_range(12000, 16000); + + /* 8192 cycles prior to first SCCB transaction */ + delay_us = mia1321_cal_delay(8192); + usleep_range(delay_us, delay_us * 2); + return 0; + +disable_clk: + clk_disable_unprepare(mia1321->xvclk); + + return ret; +} + +static void __mia1321_power_off(struct mia1321 *mia1321) +{ + int ret; + struct device *dev = &mia1321->client->dev; + + clk_disable_unprepare(mia1321->xvclk); + if (mia1321->is_thunderboot) { + if (mia1321->is_first_streamoff) { + mia1321->is_thunderboot = false; + mia1321->is_first_streamoff = false; + } else { + return; + } + } + + if (!IS_ERR(mia1321->pwdn_gpio)) + gpiod_set_value_cansleep(mia1321->pwdn_gpio, 0); + if (!IS_ERR(mia1321->reset_gpio)) + gpiod_set_value_cansleep(mia1321->reset_gpio, 0); + if (!IS_ERR_OR_NULL(mia1321->pins_sleep)) { + ret = pinctrl_select_state(mia1321->pinctrl, + mia1321->pins_sleep); + if (ret < 0) + dev_dbg(dev, "could not set pins\n"); + } + regulator_bulk_disable(MIA1321_NUM_SUPPLIES, mia1321->supplies); +} + +static int __maybe_unused mia1321_runtime_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mia1321 *mia1321 = to_mia1321(sd); + + return __mia1321_power_on(mia1321); +} + +static int __maybe_unused mia1321_runtime_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mia1321 *mia1321 = to_mia1321(sd); + + __mia1321_power_off(mia1321); + + return 0; +} + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static int mia1321_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + struct mia1321 *mia1321 = to_mia1321(sd); + struct v4l2_mbus_framefmt *try_fmt = + v4l2_subdev_get_try_format(sd, fh->pad, 0); + const struct mia1321_mode *def_mode = &supported_modes[0]; + + mutex_lock(&mia1321->mutex); + /* Initialize try_fmt */ + try_fmt->width = def_mode->width; + try_fmt->height = def_mode->height; + try_fmt->code = def_mode->bus_fmt; + try_fmt->field = V4L2_FIELD_NONE; + + mutex_unlock(&mia1321->mutex); + /* No crop or compose */ + + return 0; +} +#endif + +static int mia1321_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + if (fie->index >= ARRAY_SIZE(supported_modes)) + return -EINVAL; + + fie->code = supported_modes[fie->index].bus_fmt; + fie->width = supported_modes[fie->index].width; + fie->height = supported_modes[fie->index].height; + fie->interval = supported_modes[fie->index].max_fps; + fie->reserved[0] = supported_modes[fie->index].hdr_mode; + return 0; +} + +static const struct dev_pm_ops mia1321_pm_ops = { + SET_RUNTIME_PM_OPS(mia1321_runtime_suspend, + mia1321_runtime_resume, NULL) +}; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API +static const struct v4l2_subdev_internal_ops mia1321_internal_ops = { + .open = mia1321_open, +}; +#endif + +static const struct v4l2_subdev_core_ops mia1321_core_ops = { + .s_power = mia1321_s_power, + .ioctl = mia1321_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = mia1321_compat_ioctl32, +#endif +}; + +static const struct v4l2_subdev_video_ops mia1321_video_ops = { + .s_stream = mia1321_s_stream, + .g_frame_interval = mia1321_g_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops mia1321_pad_ops = { + .enum_mbus_code = mia1321_enum_mbus_code, + .enum_frame_size = mia1321_enum_frame_sizes, + .enum_frame_interval = mia1321_enum_frame_interval, + .get_fmt = mia1321_get_fmt, + .set_fmt = mia1321_set_fmt, + .get_mbus_config = mia1321_g_mbus_config, +}; + +static const struct v4l2_subdev_ops mia1321_subdev_ops = { + .core = &mia1321_core_ops, + .video = &mia1321_video_ops, + .pad = &mia1321_pad_ops, +}; + +/* +static void mia1321_modify_fps_info(struct mia1321 *mia1321) +{ + const struct mia1321_mode *mode = mia1321->cur_mode; + + mia1321->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def / + mia1321->cur_vts; +} +*/ + +static int mia1321_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mia1321 *mia1321 = container_of(ctrl->handler, + struct mia1321, ctrl_handler); + struct i2c_client *client = mia1321->client; + s64 max; + int ret = 0; + u32 val = 0; + //dev_info(&client->dev, "---22--gain ------------ %d--- %d--- %d\n", + // mia1321->cur_vts, mia1321->cur_mode->vts_def, mia1321->cur_mode->height); + /* Propagate change of current control to all related controls */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + /* Update max exposure while meeting expected vblanking */ + max = mia1321->cur_mode->height + ctrl->val - 1; + __v4l2_ctrl_modify_range(mia1321->exposure, + mia1321->exposure->minimum, max, + mia1321->exposure->step, + mia1321->exposure->default_value); + break; + } + + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + dev_info(&(mia1321->client->dev), "set exposure 0x%x\n", ctrl->val); + + if (mia1321->cur_mode->hdr_mode == NO_HDR) { + val = ctrl->val; + + ret = mia1321_write_reg(mia1321->client, + MIA1321_REG_EXPOSURE_H, + MIA1321_REG_VALUE_08BIT, + MIA1321_FETCH_EXP_H(val)); + ret = mia1321_write_reg(mia1321->client, + MIA1321_REG_EXPOSURE_M, + MIA1321_REG_VALUE_08BIT, + MIA1321_FETCH_EXP_M(val)); + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_EXPOSURE_L, + MIA1321_REG_VALUE_08BIT, + MIA1321_FETCH_EXP_L(val)); + } + break; + case V4L2_CID_ANALOGUE_GAIN: + dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val); + if (mia1321->cur_mode->hdr_mode == NO_HDR) + ret = mia1321_set_gain_reg(mia1321, ctrl->val); + break; + case V4L2_CID_VBLANK: + /*TODO stable vts*/ + dev_info(&(mia1321->client->dev), "set vblank 0x%x\n", ctrl->val); + /* + ret = mia1321_write_reg(mia1321->client, + MIA1321_REG_VTS_H, + MIA1321_REG_VALUE_08BIT, + (ctrl->val + mia1321->cur_mode->height) + >> 8); + ret |= mia1321_write_reg(mia1321->client, + MIA1321_REG_VTS_L, + MIA1321_REG_VALUE_08BIT, + (ctrl->val + mia1321->cur_mode->height) + & 0xff); + mia1321->cur_vts = ctrl->val + mia1321->cur_mode->height; + if (mia1321->cur_vts != mia1321->cur_mode->vts_def) + mia1321_modify_fps_info(mia1321); + */ + mia1321->cur_vts = mia1321->cur_mode->vts_def; + break; + case V4L2_CID_TEST_PATTERN: + ret = mia1321_enable_test_pattern(mia1321, ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = mia1321_read_reg(mia1321->client, MIA1321_FLIP_REG, + MIA1321_REG_VALUE_08BIT, &val); + if (ctrl->val) + val |= MIRROR_BIT_MASK; + else + val &= ~MIRROR_BIT_MASK; + mia1321_set_orientation_reg(mia1321, val); + break; + case V4L2_CID_VFLIP: + ret = mia1321_read_reg(mia1321->client, MIA1321_MIRROR_REG, + MIA1321_REG_VALUE_08BIT, &val); + if (ctrl->val) + val |= FLIP_BIT_MASK; + else + val &= ~FLIP_BIT_MASK; + mia1321_set_orientation_reg(mia1321, val); + break; + default: + dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", + __func__, ctrl->id, ctrl->val); + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops mia1321_ctrl_ops = { + .s_ctrl = mia1321_set_ctrl, +}; + +static int mia1321_initialize_controls(struct mia1321 *mia1321) +{ + const struct mia1321_mode *mode; + struct v4l2_ctrl_handler *handler; + struct v4l2_ctrl *ctrl; + s64 exposure_max, vblank_def; + u32 h_blank; + int ret; + + handler = &mia1321->ctrl_handler; + mode = mia1321->cur_mode; + ret = v4l2_ctrl_handler_init(handler, 9); + if (ret) + return ret; + handler->lock = &mia1321->mutex; + + ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, + 0, 0, link_freq_menu_items); + if (ctrl) + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, + 0, PIXEL_RATE_WITH_315M_10BIT, 1, PIXEL_RATE_WITH_315M_10BIT); + + h_blank = mode->hts_def - mode->width; + mia1321->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, + h_blank, h_blank, 1, h_blank); + if (mia1321->hblank) + mia1321->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + vblank_def = mode->vts_def - mode->height; + mia1321->vblank = v4l2_ctrl_new_std(handler, &mia1321_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + MIA1321_VTS_MAX - mode->height, + 1, vblank_def); + mia1321->cur_fps = mode->max_fps; + exposure_max = mode->vts_def - 1; + mia1321->exposure = v4l2_ctrl_new_std(handler, &mia1321_ctrl_ops, + V4L2_CID_EXPOSURE, MIA1321_EXPOSURE_MIN, + exposure_max, MIA1321_EXPOSURE_STEP, + mode->exp_def); + mia1321->anal_gain = v4l2_ctrl_new_std(handler, &mia1321_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, MIA1321_GAIN_MIN, + MIA1321_GAIN_MAX, MIA1321_GAIN_STEP, + MIA1321_GAIN_DEFAULT); + mia1321->test_pattern = v4l2_ctrl_new_std_menu_items(handler, + &mia1321_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(mia1321_test_pattern_menu) - 1, + 0, 0, mia1321_test_pattern_menu); + v4l2_ctrl_new_std(handler, &mia1321_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(handler, &mia1321_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + if (handler->error) { + ret = handler->error; + dev_err(&mia1321->client->dev, + "Failed to init controls(%d)\n", ret); + goto err_free_handler; + } + + mia1321->subdev.ctrl_handler = handler; + + return 0; + +err_free_handler: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +static int mia1321_check_sensor_id(struct mia1321 *mia1321, + struct i2c_client *client) +{ + struct device *dev = &mia1321->client->dev; + u32 id = 0; + int ret; + + if (mia1321->is_thunderboot) { + dev_info(dev, "Enable thunderboot mode, skip sensor id check\n"); + return 0; + } + + ret = mia1321_read_reg(client, MIA1321_REG_CHIP_ID, + MIA1321_REG_VALUE_16BIT, &id); + if (id != CHIP_ID) { + dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret); + return -ENODEV; + } + + dev_info(dev, "Detected MIA1321(mis%04x) sensor\n", CHIP_ID); + + return 0; +} + +static int mia1321_configure_regulators(struct mia1321 *mia1321) +{ + unsigned int i; + + for (i = 0; i < MIA1321_NUM_SUPPLIES; i++) + mia1321->supplies[i].supply = mia1321_supply_names[i]; + + return devm_regulator_bulk_get(&mia1321->client->dev, + MIA1321_NUM_SUPPLIES, + mia1321->supplies); +} + +static int mia1321_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct device_node *node = dev->of_node; + struct mia1321 *mia1321; + struct v4l2_subdev *sd; + char facing[2]; + int ret; + + dev_info(dev, "driver version: %02x.%02x.%02x", + DRIVER_VERSION >> 16, + (DRIVER_VERSION & 0xff00) >> 8, + DRIVER_VERSION & 0x00ff); + + mia1321 = devm_kzalloc(dev, sizeof(*mia1321), GFP_KERNEL); + if (!mia1321) + return -ENOMEM; + + ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX, + &mia1321->module_index); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING, + &mia1321->module_facing); + ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME, + &mia1321->module_name); + ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME, + &mia1321->len_name); + if (ret) { + dev_err(dev, "could not get module information!\n"); + return -EINVAL; + } + + mia1321->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP); + mia1321->client = client; + mia1321->cur_mode = &supported_modes[0]; + + mia1321->xvclk = devm_clk_get(dev, "xvclk"); + if (IS_ERR(mia1321->xvclk)) { + dev_err(dev, "Failed to get xvclk\n"); + return -EINVAL; + } + + if (mia1321->is_thunderboot) { + mia1321->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS); + if (IS_ERR(mia1321->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + mia1321->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS); + if (IS_ERR(mia1321->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + } else { + mia1321->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(mia1321->reset_gpio)) + dev_warn(dev, "Failed to get reset-gpios\n"); + + mia1321->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW); + if (IS_ERR(mia1321->pwdn_gpio)) + dev_warn(dev, "Failed to get pwdn-gpios\n"); + } + mia1321->pinctrl = devm_pinctrl_get(dev); + if (!IS_ERR(mia1321->pinctrl)) { + mia1321->pins_default = + pinctrl_lookup_state(mia1321->pinctrl, + OF_CAMERA_PINCTRL_STATE_DEFAULT); + if (IS_ERR(mia1321->pins_default)) + dev_err(dev, "could not get default pinstate\n"); + + mia1321->pins_sleep = + pinctrl_lookup_state(mia1321->pinctrl, + OF_CAMERA_PINCTRL_STATE_SLEEP); + if (IS_ERR(mia1321->pins_sleep)) + dev_err(dev, "could not get sleep pinstate\n"); + } else { + dev_err(dev, "no pinctrl\n"); + } + + ret = mia1321_configure_regulators(mia1321); + if (ret) { + dev_err(dev, "Failed to get power regulators\n"); + return ret; + } + + mutex_init(&mia1321->mutex); + + sd = &mia1321->subdev; + v4l2_i2c_subdev_init(sd, client, &mia1321_subdev_ops); + ret = mia1321_initialize_controls(mia1321); + if (ret) + goto err_destroy_mutex; + + ret = __mia1321_power_on(mia1321); + if (ret) + goto err_free_handler; + + ret = mia1321_check_sensor_id(mia1321, client); + if (ret) + goto err_power_off; + +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API + sd->internal_ops = &mia1321_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | + V4L2_SUBDEV_FL_HAS_EVENTS; +#endif +#if defined(CONFIG_MEDIA_CONTROLLER) + mia1321->pad.flags = MEDIA_PAD_FL_SOURCE; + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&sd->entity, 1, &mia1321->pad); + if (ret < 0) + goto err_power_off; +#endif + + memset(facing, 0, sizeof(facing)); + if (strcmp(mia1321->module_facing, "back") == 0) + facing[0] = 'b'; + else + facing[0] = 'f'; + + snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s", + mia1321->module_index, facing, + MIA1321_NAME, dev_name(sd->dev)); + ret = v4l2_async_register_subdev_sensor_common(sd); + if (ret) { + dev_err(dev, "v4l2 async register subdev failed\n"); + goto err_clean_entity; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + if (mia1321->is_thunderboot) + pm_runtime_get_sync(dev); + else + pm_runtime_idle(dev); + + return 0; + +err_clean_entity: +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif +err_power_off: + __mia1321_power_off(mia1321); +err_free_handler: + v4l2_ctrl_handler_free(&mia1321->ctrl_handler); +err_destroy_mutex: + mutex_destroy(&mia1321->mutex); + + return ret; +} + +static int mia1321_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct mia1321 *mia1321 = to_mia1321(sd); + + v4l2_async_unregister_subdev(sd); +#if defined(CONFIG_MEDIA_CONTROLLER) + media_entity_cleanup(&sd->entity); +#endif + v4l2_ctrl_handler_free(&mia1321->ctrl_handler); + mutex_destroy(&mia1321->mutex); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + __mia1321_power_off(mia1321); + pm_runtime_set_suspended(&client->dev); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id mia1321_of_match[] = { + { .compatible = "imagedesign,mia1321" }, + {}, +}; +MODULE_DEVICE_TABLE(of, mia1321_of_match); +#endif + +static const struct i2c_device_id mia1321_match_id[] = { + { "imagedesign,mia1321", 0 }, + { }, +}; + +static struct i2c_driver mia1321_i2c_driver = { + .driver = { + .name = MIA1321_NAME, + .pm = &mia1321_pm_ops, + .of_match_table = of_match_ptr(mia1321_of_match), + }, + .probe = &mia1321_probe, + .remove = &mia1321_remove, + .id_table = mia1321_match_id, +}; + +static int __init sensor_mod_init(void) +{ + return i2c_add_driver(&mia1321_i2c_driver); +} + +static void __exit sensor_mod_exit(void) +{ + i2c_del_driver(&mia1321_i2c_driver); +} + +#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC) +subsys_initcall(sensor_mod_init); +#else +device_initcall_sync(sensor_mod_init); +#endif +module_exit(sensor_mod_exit); + +MODULE_DESCRIPTION("imagedesign mia1321 sensor driver"); +MODULE_LICENSE("GPL"); + diff --git a/sysdrv/source/kernel/drivers/media/platform/rockchip/isp/hw.c b/sysdrv/source/kernel/drivers/media/platform/rockchip/isp/hw.c index af811e271..131a4e2f6 100644 --- a/sysdrv/source/kernel/drivers/media/platform/rockchip/isp/hw.c +++ b/sysdrv/source/kernel/drivers/media/platform/rockchip/isp/hw.c @@ -1076,6 +1076,7 @@ static int rkisp_hw_probe(struct platform_device *pdev) struct resource *res; int i, ret, mult = 1; bool is_mem_reserved = true; + u32 unite_state; u32 clk_rate = 0; match = of_match_node(rkisp_hw_of_match, node); @@ -1146,6 +1147,11 @@ static int rkisp_hw_probe(struct platform_device *pdev) hw_dev->isp_ver = match_data->isp_ver; if (match_data->unite) { hw_dev->unite = ISP_UNITE_TWO; + } else if (!device_property_read_u32(dev, "rockchip,unite", &unite_state)) { + if ( unite_state == 1 ) { + hw_dev->unite = ISP_UNITE_ONE; + hw_dev->base_next_addr = hw_dev->base_addr; + } } else if (device_property_read_bool(dev, "rockchip,unite-en")) { hw_dev->unite = ISP_UNITE_ONE; hw_dev->base_next_addr = hw_dev->base_addr; diff --git a/sysdrv/tools/board/buildroot/luckfox_pico_defconfig b/sysdrv/tools/board/buildroot/luckfox_pico_defconfig index 0e94cc3de..4cc92d1f4 100755 --- a/sysdrv/tools/board/buildroot/luckfox_pico_defconfig +++ b/sysdrv/tools/board/buildroot/luckfox_pico_defconfig @@ -40,6 +40,7 @@ BR2_PACKAGE_DTC=y BR2_PACKAGE_DTC_PROGRAMS=y BR2_PACKAGE_LIBV4L=y BR2_PACKAGE_LIBV4L_UTILS=y +BR2_PACKAGE_LIBRSYNC=y BR2_PACKAGE_PCRE2=y BR2_PACKAGE_PCRE2_16=y BR2_PACKAGE_PCRE2_32=y @@ -48,6 +49,7 @@ BR2_PACKAGE_IPERF3=y BR2_PACKAGE_LRZSZ=y BR2_PACKAGE_NTP=y BR2_PACKAGE_OPENSSH=y +BR2_PACKAGE_RSYNC=y BR2_PACKAGE_SOCAT=y BR2_PACKAGE_BASH=y BR2_PACKAGE_BASH_LOADABLE_EXAMPLES=y