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Second round to make it work for ESP32S3.

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Signed-off-by: Pol Henarejos <pol.henarejos@cttc.es>
This commit is contained in:
Pol Henarejos
2024-04-08 16:47:16 +02:00
parent 49f05e9e13
commit 06fd241f49
13 changed files with 196 additions and 164 deletions
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28
src/usb/tusb_config.h
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@@ -45,7 +45,7 @@ extern "C" {
#endif
//--------------------------------------------------------------------
// COMMON CONFIGURATION
// Common Configuration
//--------------------------------------------------------------------
// defined by compiler flags for flexibility
@@ -53,20 +53,20 @@ extern "C" {
#error CFG_TUSB_MCU must be defined
#endif
#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || \
CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56
#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
#else
#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE
#ifndef CFG_TUSB_OS
#if CFG_TUSB_MCU == OPT_MCU_RP2040
#define CFG_TUSB_OS OPT_OS_PICO
#elif CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
#define CFG_TUSB_OS OPT_OS_FREERTOS
#endif
#endif
#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS OPT_OS_FREERTOS
#ifndef CFG_TUSB_RHPORT0_MODE
#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_FULL_SPEED)
#endif
#ifndef CFG_TUSB_DEBUG
#define CFG_TUSB_DEBUG 1
#define CFG_TUSB_DEBUG 0
#endif
// Enable Device stack
@@ -113,11 +113,17 @@ extern "C" {
#ifdef USB_ITF_CCID
#define CFG_TUD_VENDOR 2
#else
#define CFG_TUD_VENDOR 2
#define CFG_TUD_VENDOR 0
#endif
// HID buffer size Should be sufficient to hold ID (if any) + Data
#define CFG_TUD_HID_EP_BUFSIZE 64
// CDC FIFO size of TX and RX
#define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
// CDC Endpoint transfer buffer size, more is faster
#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#ifdef __cplusplus
}