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update:add luckfox-pico Ultra support

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This commit is contained in:
luckfox-eng29
2024-03-16 17:03:10 +08:00
committed by luckfox-eng33
parent 1e160dee55
commit d3153ac97e
234 changed files with 89019 additions and 2435 deletions
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153
sysdrv/source/kernel/arch/arm/boot/dts/rv1103-luckfox-pico-ipc.dtsi Normal file → Executable file
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@@ -54,8 +54,27 @@
gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "activity";
default-state = "on";
};
};
};
// DHT11
dht11_sensor {
compatible = "dht11";
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pc7>;
dht11@1 {
gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
label = "dht11";
linux,default-trigger = "humidity";
};
};
};
/***************************** AUDIO ********************************/
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&acodec {
@@ -64,10 +83,40 @@
status = "okay";
};
/***************************** CPU ********************************/
&cpu0 {
cpu-supply = <&vdd_arm>;
};
/***************************** ADC ********************************/
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&tsadc {
status = "okay";
};
/***************************** USB *********************************/
&u2phy {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usbdrd {
status = "okay";
};
&usbdrd_dwc3 {
extcon = <&u2phy>;
status = "okay";
};
/*****************************CSI ********************************/
&csi2_dphy_hw {
status = "okay";
};
@@ -186,11 +235,6 @@
};
};
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&mipi0_csi2 {
status = "okay";
@@ -222,10 +266,6 @@
};
};
&pwm0 {
status = "okay";
};
&rkcif {
status = "okay";
};
@@ -268,25 +308,84 @@
};
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
/***************************** PINCTRL ********************************/
// SPI
&spi0 {
pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>;
};
// I2C
&i2c3 {
pinctrl-0 = <&i2c3m1_xfer>;
};
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
};
// UART
&uart3 {
pinctrl-0 = <&uart3m1_xfer>;
};
&uart4 {
pinctrl-0 = <&uart4m1_xfer>;
};
&uart5 {
pinctrl-0 = <&uart5m0_xfer>;
};
&sdmmc {
max-frequency = <50000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
status = "okay";
// PWM
&pwm0 {
pinctrl-0 = <&pwm0m0_pins &pwm0m1_pins>;
};
&pwm1 {
pinctrl-0 = <&pwm1m0_pins>;
};
&pwm2 {
pinctrl-0 = <&pwm2m2_pins>;
};
&pwm3 {
pinctrl-0 = <&pwm3m2_pins>;
};
&pwm4 {
pinctrl-0 = <&pwm4m2_pins>;
};
&pwm5 {
pinctrl-0 = <&pwm5m2_pins>;
};
&pwm6 {
pinctrl-0 = <&pwm6m2_pins>;
};
&pwm8 {
pinctrl-0 = <&pwm8m0_pins &pwm8m1_pins>;
};
&pwm9 {
pinctrl-0 = <&pwm9m0_pins &pwm9m1_pins>;
};
&pwm10 {
pinctrl-0 = <&pwm10m0_pins &pwm10m1_pins>;
};
&pwm11 {
pinctrl-0 = <&pwm11m0_pins &pwm11m1_pins>;
};
&tsadc {
status = "okay";
};
&pinctrl {
spi0 {
spi0m0_clk: spi0m0-clk {
rockchip,pins = <1 RK_PC1 4 &pcfg_pull_none>;
};
spi0m0_mosi: spi0m0-mosi {
rockchip,pins = <1 RK_PC2 6 &pcfg_pull_none>;
};
spi0m0_miso: spi0m0-miso {
rockchip,pins = <1 RK_PC3 6 &pcfg_pull_none>;
};
spi0m0_cs0: spi0m0-cs0 {
rockchip,pins = <1 RK_PC0 4 &pcfg_pull_none>;
};
};
gpio1-pc7 {
gpio1_pc7:gpio1-pc7 {
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

280
sysdrv/source/kernel/arch/arm/boot/dts/rv1103-luckfox-pico-mini-ipc.dtsi
View File

@@ -1,280 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-amp.dtsi"
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk1p7 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0";
};
acodec_sound: acodec-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rv-acodec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
simple-audio-card,codec {
sound-dai = <&acodec>;
};
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_arm: vdd-arm {
compatible = "regulator-fixed";
regulator-name = "vdd_arm";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
leds: leds {
compatible = "gpio-leds";
work_led: work{
gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "activity";
default-state = "on";
};
};
};
&acodec {
#sound-dai-cells = <0>;
pa-ctl-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input0: endpoint@0 {
reg = <0>;
remote-endpoint = <&sc3336_out>;
data-lanes = <1 2>;
};
csi_dphy_input1: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc4336_out>;
data-lanes = <1 2>;
};
csi_dphy_input2: endpoint@2 {
reg = <2>;
remote-endpoint = <&sc530ai_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4m2_xfer>;
sc3336: sc3336@30 {
compatible = "smartsens,sc3336";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2119-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc3336_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2>;
};
};
};
sc4336: sc4336@30 {
compatible = "smartsens,sc4336";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "OT01";
rockchip,camera-module-lens-name = "40IRC_F16";
port {
sc4336_out: endpoint {
remote-endpoint = <&csi_dphy_input1>;
data-lanes = <1 2>;
};
};
};
sc530ai: sc530ai@30 {
compatible = "smartsens,sc530ai";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2115-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc530ai_out: endpoint {
remote-endpoint = <&csi_dphy_input2>;
data-lanes = <1 2>;
};
};
};
};
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
//&pwm0 {
// status = "okay";
//};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&tsadc {
status = "okay";
};

277
sysdrv/source/kernel/arch/arm/boot/dts/rv1103-luckfox-pico-plus-ipc.dtsi
View File

@@ -1,277 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-amp.dtsi"
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk1p7 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0";
};
acodec_sound: acodec-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rv-acodec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
simple-audio-card,codec {
sound-dai = <&acodec>;
};
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_arm: vdd-arm {
compatible = "regulator-fixed";
regulator-name = "vdd_arm";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
leds: leds {
compatible = "gpio-leds";
work_led: work{
gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "activity";
default-state = "on";
};
};
};
&acodec {
#sound-dai-cells = <0>;
pa-ctl-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input0: endpoint@0 {
reg = <0>;
remote-endpoint = <&sc3336_out>;
data-lanes = <1 2>;
};
csi_dphy_input1: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc4336_out>;
data-lanes = <1 2>;
};
csi_dphy_input2: endpoint@2 {
reg = <2>;
remote-endpoint = <&sc530ai_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4m2_xfer>;
sc3336: sc3336@30 {
compatible = "smartsens,sc3336";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2119-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc3336_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2>;
};
};
};
sc4336: sc4336@30 {
compatible = "smartsens,sc4336";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "OT01";
rockchip,camera-module-lens-name = "40IRC_F16";
port {
sc4336_out: endpoint {
remote-endpoint = <&csi_dphy_input1>;
data-lanes = <1 2>;
};
};
};
sc530ai: sc530ai@30 {
compatible = "smartsens,sc530ai";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2115-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc530ai_out: endpoint {
remote-endpoint = <&csi_dphy_input2>;
data-lanes = <1 2>;
};
};
};
};
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&tsadc {
status = "okay";
};

133
sysdrv/source/kernel/arch/arm/boot/dts/rv1103g-luckfox-pico-mini-a.dts
View File

@@ -7,7 +7,7 @@
#include "rv1103.dtsi"
#include "rv1106-evb.dtsi"
#include "rv1103-luckfox-pico-mini-ipc.dtsi"
#include "rv1103-luckfox-pico-ipc.dtsi"
/ {
model = "Luckfox Pico Mini A";
@@ -34,129 +34,44 @@
};
/**********USB**********/
//&usbdrd {
// status = "disabled";
//};
//&usbdrd_dwc3 {
// status = "disabled";
//};
//&u2phy {
// status = "disabled";
//};
//&u2phy_otg {
// status = "disabled";
//};
// /**********I2C**********/
&i2c3 {
&usbdrd_dwc3 {
status = "okay";
pinctrl-0 = <&i2c3m1_xfer>;
clock-frequency = <100000>;
dr_mode = "peripheral";
};
// /**********SPI**********/
/**********SPI**********/
/* SPI0_M0 */
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
cs-gpios = <&gpio1 RK_PC0 1>;
// cs-gpios = <&gpio1 RK_PD3 1>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <1000000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};
/**********UART**********/
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
/**********I2C**********/
/* I2C3_M1 */
&i2c3 {
status = "disabled";
clock-frequency = <100000>;
};
/**********UART**********/
/* UART3_M1 */
&uart3 {
status = "disabled";
};
/* UART4_M1 */
&uart4 {
status = "disabled";
};
/**********PWM**********/
// &pwm0 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm0m0_pins>;
// // pinctrl-0 = <&pwm0m1_pins>;
// };
// &pwm1 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm1m0_pins>;
// // pinctrl-0 = <&pwm1m1_pins>;
// };
//&pwm2 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm2m2_pins>;
//};
//&pwm3 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm3m2_pins>;
//};
//&pwm4 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm4m2_pins>;
//};
//&pwm5 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm5m2_pins>;
//};
//&pwm6 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm6m2_pins>;
//};
//&pwm7 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm7m2_pins>;
//};
//&pwm8 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm8m1_pins>;
// pinctrl-0 = <&pwm8m0_pins>;
//};
//&pwm9 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm9m1_pins>;
// pinctrl-0 = <&pwm9m0_pins>;
//};
&pwm10 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm10m1_pins>;
// pinctrl-0 = <&pwm10m2_pins>;
// pinctrl-0 = <&pwm10m0_pins>;
/* PWM1_M0 */
&pwm1 {
status = "disabled";
};
&pwm11 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm11m1_pins>;
// pinctrl-0 = <&pwm11m2_pins>;
// pinctrl-0 = <&pwm11m0_pins>;
};

136
sysdrv/source/kernel/arch/arm/boot/dts/rv1103g-luckfox-pico-mini-b.dts
View File

@@ -14,6 +14,7 @@
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1103";
};
/**********SFC**********/
&sfc {
status = "okay";
flash@0 {
@@ -24,6 +25,7 @@
spi-tx-bus-width = <1>;
};
};
/**********SDMMC**********/
&sdmmc {
max-frequency = <50000000>;
@@ -37,135 +39,51 @@
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
status = "okay";
};
// /**********ETH**********/
/**********ETH**********/
&gmac {
status = "disabled";
};
/**********USB**********/
//&usbdrd {
// status = "disabled";
//};
//&usbdrd_dwc3 {
// status = "disabled";
//};
//&u2phy {
// status = "disabled";
//};
//&u2phy_otg {
// status = "disabled";
//};
// /**********I2C**********/
&i2c3 {
&usbdrd_dwc3 {
status = "okay";
pinctrl-0 = <&i2c3m1_xfer>;
clock-frequency = <100000>;
dr_mode = "peripheral";
};
// /**********SPI**********/
/**********SPI**********/
/* SPI0_M0 */
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
cs-gpios = <&gpio1 RK_PC0 1>;
// cs-gpios = <&gpio1 RK_PD3 1>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <1000000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};
/**********UART**********/
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
/**********I2C**********/
/* I2C3_M1 */
&i2c3 {
status = "disabled";
clock-frequency = <100000>;
};
/**********UART**********/
/* UART3_M1 */
&uart3 {
status = "disabled";
};
/* UART4_M1 */
&uart4 {
status = "disabled";
};
/**********PWM**********/
// &pwm0 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm0m0_pins>;
// // pinctrl-0 = <&pwm0m1_pins>;
// };
// &pwm1 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm1m0_pins>;
// // pinctrl-0 = <&pwm1m1_pins>;
// };
//&pwm2 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm2m2_pins>;
//};
//&pwm3 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm3m2_pins>;
//};
//&pwm4 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm4m2_pins>;
//};
//&pwm5 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm5m2_pins>;
//};
//&pwm6 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm6m2_pins>;
//};
//&pwm7 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm7m2_pins>;
//};
//&pwm8 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm8m1_pins>;
// pinctrl-0 = <&pwm8m0_pins>;
//};
//&pwm9 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm9m1_pins>;
// pinctrl-0 = <&pwm9m0_pins>;
//};
&pwm10 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm10m1_pins>;
// pinctrl-0 = <&pwm10m2_pins>;
// pinctrl-0 = <&pwm10m0_pins>;
/* PWM1_M0 */
&pwm1 {
status = "disabled";
};
&pwm11 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm11m1_pins>;
// pinctrl-0 = <&pwm11m2_pins>;
// pinctrl-0 = <&pwm11m0_pins>;
};

185
sysdrv/source/kernel/arch/arm/boot/dts/rv1103g-luckfox-pico-plus-sd.dts
View File

@@ -1,185 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1103.dtsi"
#include "rv1106-evb.dtsi"
#include "rv1103-luckfox-pico-plus-ipc.dtsi"
/ {
model = "Luckfox Pico Plus";
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1103";
};
/**********SDMMC**********/
&sdmmc {
max-frequency = <50000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
status = "okay";
};
/**********SFC**********/
&sfc {
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <75000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
/**********ETH**********/
&gmac {
status = "okay";
};
/**********USB**********/
//&usbdrd {
// status = "disabled";
//};
//&usbdrd_dwc3 {
// status = "disabled";
//};
//&u2phy {
// status = "disabled";
//};
//&u2phy_otg {
// status = "disabled";
//};
/**********I2C**********/
// &i2c0 {
// status = "okay";
// pinctrl-0 = <&i2c0m2_xfer>;
// clock-frequency = <100000>;
// };
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3m1_xfer>;
clock-frequency = <100000>;
};
/**********SPI**********/
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
cs-gpios = <&gpio1 RK_PC0 1>;
// cs-gpios = <&gpio1 26 1>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <1000000000>;
reg = <0>;
};
};
/**********UART**********/
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
};
//&uart5 {
// status = "okay";
// pinctrl-names = "default";
// pinctrl-0 = <&uart5m0_xfer>;
//};
/**********PWM**********/
&pwm0 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm0m0_pins>;
// pinctrl-0 = <&pwm0m1_pins>;
};
&pwm1 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm1m0_pins>;
// pinctrl-0 = <&pwm1m1_pins>;
};
//&pwm2 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm2m2_pins>;
//};
//&pwm3 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm3m2_pins>;
//};
//&pwm4 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm4m2_pins>;
//};
//&pwm5 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm5m2_pins>;
//};
//&pwm6 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm6m2_pins>;
//};
//&pwm7 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm7m2_pins>;
//};
//&pwm8 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm8m1_pins>;
// pinctrl-0 = <&pwm8m0_pins>;
//};
//&pwm9 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm9m1_pins>;
// pinctrl-0 = <&pwm9m0_pins>;
//};
&pwm10 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm10m1_pins>;
// pinctrl-0 = <&pwm10m2_pins>;
// pinctrl-0 = <&pwm10m0_pins>;
};
&pwm11 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm11m1_pins>;
// pinctrl-0 = <&pwm11m2_pins>;
// pinctrl-0 = <&pwm11m0_pins>;
};

251
sysdrv/source/kernel/arch/arm/boot/dts/rv1103g-luckfox-pico-plus.dts Normal file → Executable file
View File

@@ -7,115 +7,16 @@
#include "rv1103.dtsi"
#include "rv1106-evb.dtsi"
#include "rv1103-luckfox-pico-plus-ipc.dtsi"
#include "rv1103-luckfox-pico-ipc.dtsi"
/ {
model = "Luckfox Pico Plus";
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1103";
gpio3pa1:gpio3pa1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pa1>;
regulator-name = "gpio3_pa1";
regulator-always-on;
};
gpio3pa2:gpio3pa2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pa2>;
regulator-name = "gpio3_pa2";
regulator-always-on;
};
gpio3pa3:gpio3pa3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pa3>;
regulator-name = "gpio3_pa3";
regulator-always-on;
};
gpio3pa4:gpio3pa4 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pa4>;
regulator-name = "gpio3_pa4";
regulator-always-on;
};
gpio3pa5:gpio3pa5 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pa5>;
regulator-name = "gpio3_pa5";
regulator-always-on;
};
gpio3pa6:gpio3pa6 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pa6>;
regulator-name = "gpio3_pa6";
regulator-always-on;
};
gpio3pa7:gpio3pa7 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio3_pa7>;
regulator-name = "gpio3_pa7";
regulator-always-on;
};
};
/**********GPIO**********/
&pinctrl {
gpio3-pa1 {
gpio3_pa1:gpio3-pa1 {
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio3-pa2 {
gpio3_pa2:gpio3-pa2 {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio3-pa3 {
gpio3_pa3:gpio3-pa3 {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio3-pa4 {
gpio3_pa4:gpio3-pa4 {
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio3-pa5 {
gpio3_pa5:gpio3-pa5 {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio3-pa6 {
gpio3_pa6:gpio3-pa6 {
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio3-pa7 {
gpio3_pa7:gpio3-pa7 {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
/**********SFC**********/
&sfc {
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
@@ -125,144 +26,72 @@
};
};
/**********SDMMC**********/
&sdmmc {
max-frequency = <50000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
status = "okay";
};
/**********ETH**********/
&gmac {
status = "okay";
};
/**********USB**********/
//&usbdrd {
// status = "disabled";
//};
//&usbdrd_dwc3 {
// status = "disabled";
//};
//&u2phy {
// status = "disabled";
//};
//&u2phy_otg {
// status = "disabled";
//};
/**********I2C**********/
// &i2c0 {
// status = "okay";
// pinctrl-0 = <&i2c0m2_xfer>;
// clock-frequency = <100000>;
// };
&i2c3 {
&usbdrd_dwc3 {
status = "okay";
pinctrl-0 = <&i2c3m1_xfer>;
clock-frequency = <100000>;
dr_mode = "peripheral";
};
/**********SPI**********/
/* SPI0_M0 */
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
cs-gpios = <&gpio1 RK_PC0 1>;
// cs-gpios = <&gpio1 26 1>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <1000000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};
/**********I2C**********/
/* I2C3_M1 */
&i2c3 {
status = "disabled";
clock-frequency = <100000>;
};
/* I2C0_M2 */
&i2c0 {
status = "disabled";
clock-frequency = <100000>;
};
/**********UART**********/
/* UART3_M1 */
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
status = "disabled";
};
/* UART4_M1 */
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
status = "disabled";
};
//&uart5 {
// status = "okay";
// pinctrl-names = "default";
// pinctrl-0 = <&uart5m0_xfer>;
//};
/**********PWM**********/
&pwm0 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm0m0_pins>;
// pinctrl-0 = <&pwm0m1_pins>;
};
/* PWM1_M0 */
&pwm1 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm1m0_pins>;
// pinctrl-0 = <&pwm1m1_pins>;
};
//&pwm2 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm2m2_pins>;
//};
//&pwm3 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm3m2_pins>;
//};
//&pwm4 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm4m2_pins>;
//};
//&pwm5 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm5m2_pins>;
//};
//&pwm6 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm6m2_pins>;
//};
//&pwm7 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm7m2_pins>;
//};
//&pwm8 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm8m1_pins>;
// pinctrl-0 = <&pwm8m0_pins>;
//};
//&pwm9 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm9m1_pins>;
// pinctrl-0 = <&pwm9m0_pins>;
//};
&pwm10 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm10m1_pins>;
// pinctrl-0 = <&pwm10m2_pins>;
// pinctrl-0 = <&pwm10m0_pins>;
};
&pwm11 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm11m1_pins>;
// pinctrl-0 = <&pwm11m2_pins>;
// pinctrl-0 = <&pwm11m0_pins>;
status = "disabled";
};

239
sysdrv/source/kernel/arch/arm/boot/dts/rv1103g-luckfox-pico.dts Normal file → Executable file
View File

@@ -12,102 +12,21 @@
/ {
model = "Luckfox Pico";
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1103";
gpio4pa2:gpio4pa2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio4_pa2>;
regulator-name = "gpio4_pa2";
regulator-always-on;
};
gpio4pa3:gpio4pa3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio4_pa3>;
regulator-name = "gpio4_pa3";
regulator-always-on;
};
gpio4pa4:gpio4pa4 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio4_pa4>;
regulator-name = "gpio4_pa4";
regulator-always-on;
};
gpio4pa6:gpio4pa6 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio4_pa6>;
regulator-name = "gpio4_pa6";
regulator-always-on;
};
gpio4pb0:gpio4pb0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio4_pb0>;
regulator-name = "gpio4_pb0";
regulator-always-on;
};
gpio4pb1:gpio4pb1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&gpio4_pb1>;
regulator-name = "gpio4_pb1";
regulator-always-on;
};
};
/**********GPIO**********/
&pinctrl {
gpio4-pa2 {
gpio4_pa2:gpio4-pa2 {
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio4-pa3 {
gpio4_pa3:gpio4-pa3 {
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio4-pa4 {
gpio4_pa4:gpio4-pa4 {
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio4-pa6 {
gpio4_pa6:gpio4-pa6 {
rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio4-pb0 {
gpio4_pb0:gpio4-pb0 {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
gpio4-pb1 {
gpio4_pb1:gpio4-pb1 {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
/**********SDMMC**********/
&sdmmc {
max-frequency = <50000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
status = "okay";
};
/**********ETH**********/
&gmac {
@@ -115,138 +34,46 @@
};
/**********USB**********/
// &usbdrd {
// status = "disabled";
// };
// &usbdrd_dwc3 {
// status = "disabled";
// };
// &u2phy {
// status = "disabled";
// };
// &u2phy_otg {
// status = "disabled";
// };
/**********I2C**********/
// &i2c0 {
// status = "okay";
// pinctrl-0 = <&i2c0m2_xfer>;
// clock-frequency = <100000>;
// };
&i2c3 {
&usbdrd_dwc3 {
status = "okay";
pinctrl-0 = <&i2c3m1_xfer>;
clock-frequency = <100000>;
dr_mode = "peripheral";
};
// /**********SPI**********/
/**********SPI**********/
/* SPI0_M0 */
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
cs-gpios = <&gpio1 RK_PC0 1>;
// cs-gpios = <&gpio1 26 1>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <1000000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};
// /**********UART**********/
/**********I2C**********/
/* I2C3_M1 */
&i2c3 {
status = "disabled";
clock-frequency = <100000>;
};
/**********UART**********/
/* UART3_M1 */
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
status = "disabled";
};
/* UART4_M1 */
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
status = "disabled";
};
// &uart5 {
// status = "okay";
// pinctrl-names = "default";
// pinctrl-0 = <&uart5m0_xfer>;
// };
/**********PWM**********/
&pwm0 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm0m0_pins>;
// pinctrl-0 = <&pwm0m1_pins>;
};
/* PWM1_M0 */
&pwm1 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm1m0_pins>;
// pinctrl-0 = <&pwm1m1_pins>;
};
// &pwm2 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm2m2_pins>;
// };
// &pwm3 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm3m2_pins>;
// };
// &pwm4 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm4m2_pins>;
// };
// &pwm5 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm5m2_pins>;
// };
// &pwm6 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm6m2_pins>;
// };
// &pwm7 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm7m2_pins>;
// };
// &pwm8 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm8m1_pins>;
// pinctrl-0 = <&pwm8m0_pins>;
// };
// &pwm9 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm9m1_pins>;
// pinctrl-0 = <&pwm9m0_pins>;
// };
&pwm10 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm10m1_pins>;
// pinctrl-0 = <&pwm10m2_pins>;
// pinctrl-0 = <&pwm10m0_pins>;
};
&pwm11 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm11m1_pins>;
// pinctrl-0 = <&pwm11m2_pins>;
// pinctrl-0 = <&pwm11m0_pins>;
status = "disabled";
};

139
sysdrv/source/kernel/arch/arm/boot/dts/rv1106-luckfox-pico-pro-max-ipc.dtsi
View File

@@ -57,6 +57,26 @@
default-state = "on";
};
};
// DHT11
dht11_sensor {
compatible = "dht11";
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pc7>;
dht11@1 {
gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
label = "dht11";
linux,default-trigger = "humidity";
};
};
};
/***************************** AUDIO ********************************/
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&acodec {
@@ -64,11 +84,22 @@
pa-ctl-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
/***************************** CPU ********************************/
&cpu0 {
cpu-supply = <&vdd_arm>;
};
/***************************** ADC ********************************/
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&tsadc {
status = "okay";
};
/***************************** CSI ********************************/
&csi2_dphy_hw {
status = "okay";
};
@@ -187,11 +218,6 @@
};
};
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&mipi0_csi2 {
status = "okay";
@@ -265,14 +291,99 @@
};
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&tsadc {
status = "okay";
/*****************************PINCTRL********************************/
// SPI
&spi0 {
pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>;
};
// I2C
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
};
&i2c1 {
pinctrl-0 = <&i2c1m1_xfer>;
};
&i2c3 {
pinctrl-0 = <&i2c3m1_xfer &i2c3m0_xfer>;
};
&i2c4 {
pinctrl-0 = <&i2c4m0_xfer>;
};
// UART
&uart0 {
pinctrl-0 = <&uart0m0_xfer &uart0m1_xfer>;
};
&uart1 {
pinctrl-0 = <&uart1m1_xfer>;
};
&uart3 {
pinctrl-0 = <&uart3m1_xfer>;
};
&uart4 {
pinctrl-0 = <&uart4m1_xfer>;
};
&uart5 {
pinctrl-0 = <&uart5m0_xfer>;
};
// PWM
&pwm0 {
pinctrl-0 = <&pwm0m1_pins>;
};
&pwm2 {
pinctrl-0 = <&pwm2m2_pins>;
};
&pwm3 {
pinctrl-0 = <&pwm3m2_pins>;
};
&pwm4 {
pinctrl-0 = <&pwm4m2_pins>;
};
&pwm5 {
pinctrl-0 = <&pwm5m2_pins>;
};
&pwm6 {
pinctrl-0 = <&pwm6m1_pins &pwm6m2_pins>;
};
&pwm8 {
pinctrl-0 = <&pwm8m1_pins>;
};
&pwm9 {
pinctrl-0 = <&pwm9m1_pins>;
};
&pwm10 {
pinctrl-0 = <&pwm10m2_pins>;
};
&pwm11 {
pinctrl-0 = <&pwm11m1_pins>;
};
&pinctrl {
spi0 {
spi0m0_clk: spi0m0-clk {
rockchip,pins = <1 RK_PC1 4 &pcfg_pull_none>;
};
spi0m0_mosi: spi0m0-mosi {
rockchip,pins = <1 RK_PC2 6 &pcfg_pull_none>;
};
spi0m0_miso: spi0m0-miso {
rockchip,pins = <1 RK_PC3 6 &pcfg_pull_none>;
};
spi0m0_cs0: spi0m0-cs0 {
rockchip,pins = <1 RK_PC0 4 &pcfg_pull_none>;
};
};
gpio1-pc7 {
gpio1_pc7:gpio1-pc7 {
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

564
sysdrv/source/kernel/arch/arm/boot/dts/rv1106-luckfox-pico-ultra-ipc.dtsi Executable file
View File

@@ -0,0 +1,564 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-amp.dtsi"
#include "rv1106-evb.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/display/media-bus-format.h>
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk0p7 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0";
};
backlight: backlight {
status = "okay";
compatible = "pwm-backlight";
pwms = <&pwm1 0 25000 12500>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <255>;
};
panel: panel {
compatible = "simple-panel";
backlight = <&backlight>;
//reset-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
//reset-delay-ms = <200>;
enable-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
enable-delay-ms = <20>;
status = "okay";
bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
width-mm = <85>;
height-mm = <85>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <16500000>;
hactive = <0>;
vactive = <0>;
hback-porch = <0>;
hfront-porch = <0>;
vback-porch = <0>;
vfront-porch = <0>;
hsync-len = <0>;
vsync-len = <0>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_rgb: endpoint {
remote-endpoint = <&rgb_out_panel>;
};
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
linux,cma {
compatible = "shared-dma-pool";
inactive;
reusable;
size = <0xA00000>;
linux,cma-default;
};
};
acodec_sound: acodec-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rv1106-acodec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
simple-audio-card,codec {
sound-dai = <&acodec>;
};
};
dsm_sound: dsm-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,dsm-sound";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&i2s0_8ch>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&dsm>;
};
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_arm: vdd-arm {
compatible = "regulator-fixed";
regulator-name = "vdd_arm";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
leds: leds {
compatible = "gpio-leds";
work_led: work{
gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "activity";
default-state = "on";
};
};
};
/***************************** audio ********************************/
&i2s0_8ch {
#sound-dai-cells = <0>;
status = "okay";
};
&acodec {
#sound-dai-cells = <0>;
pa-ctl-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH &pcfg_pull_up>;
status = "okay";
};
/************************* FIQ_DUBUGGER ****************************/
&fiq_debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";
};
/***************************** USB *********************************/
&u2phy {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usbdrd {
status = "okay";
};
&usbdrd_dwc3 {
extcon = <&u2phy>;
status = "okay";
};
/***************************** DSM *********************************/
&dsm {
status = "disabled";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
/*************************** CSI *********************************/
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input0: endpoint@0 {
reg = <0>;
remote-endpoint = <&sc3336_out>;
data-lanes = <1 2>;
};
csi_dphy_input1: endpoint@1 {
reg = <1>;
remote-endpoint = <&sc4336_out>;
data-lanes = <1 2>;
};
csi_dphy_input2: endpoint@2 {
reg = <2>;
remote-endpoint = <&sc530ai_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4m2_xfer>;
sc3336: sc3336@30 {
compatible = "smartsens,sc3336";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2119-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc3336_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2>;
};
};
};
sc4336: sc4336@30 {
compatible = "smartsens,sc4336";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "OT01";
rockchip,camera-module-lens-name = "40IRC_F16";
port {
sc4336_out: endpoint {
remote-endpoint = <&csi_dphy_input1>;
data-lanes = <1 2>;
};
};
};
sc530ai: sc530ai@30 {
compatible = "smartsens,sc530ai";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2115-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc530ai_out: endpoint {
remote-endpoint = <&csi_dphy_input2>;
data-lanes = <1 2>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
/***************************** ADC ********************************/
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&tsadc {
status = "okay";
};
/**************************** LCD/TP ******************************/
&pwm1 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm1m2_pins>;
};
&display_subsystem {
status = "okay";
logo-memory-region = <&drm_logo>;
};
&rgb {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
ports {
rgb_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
rgb_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_rgb>;
};
};
};
};
&rgb_in_vop {
status = "okay";
};
&route_rgb {
status = "okay";
};
&vop {
status = "okay";
};
/**************************** PINCTRL ******************************/
// SPI
&spi0 {
pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
// I2C
&i2c1 {
pinctrl-0 = <&i2c1m1_xfer>;
};
&i2c2 {
pinctrl-0 = <&i2c2m0_xfer>;
};
&i2c3 {
pinctrl-0 = <&i2c3m0_xfer &i2c3m1_xfer &i2c3m2_xfer>;
};
// &i2c4 {
// pinctrl-0 = <&i2c4m0_xfer &i2c4m1_xfer &i2c4m2_xfer>;
// };
// UART
&uart0 {
pinctrl-0 = <&uart0m0_xfer &uart0m1_xfer>;
};
&uart1 {
pinctrl-0 = <&uart1m1_xfer>;
};
&uart3 {
pinctrl-0 = <&uart3m0_xfer>;
};
&uart4 {
pinctrl-0 = <&uart4m0_xfer>;
};
&uart5 {
pinctrl-0 = <&uart5m1_xfer>;
};
// PWM
&pwm0 {
pinctrl-0 = <&pwm0m1_pins>;
};
&pwm2 {
pinctrl-0 = <&pwm2m1_pins &pwm2m2_pins>;
};
&pwm3 {
pinctrl-0 = <&pwm3m2_pins>;
};
&pwm4 {
pinctrl-0 = <&pwm4m0_pins &pwm4m1_pins &pwm4m2_pins>;
};
&pwm5 {
pinctrl-0 = <&pwm5m1_pins &pwm5m2_pins>;
};
&pwm6 {
pinctrl-0 = <&pwm6m1_pins &pwm6m2_pins>;
};
&pwm7 {
pinctrl-0 = <&pwm7m0_pins &pwm7m1_pins>;
};
&pwm8 {
pinctrl-0 = <&pwm8m1_pins>;
};
&pwm9 {
pinctrl-0 = <&pwm9m1_pins>;
};
&pwm10 {
pinctrl-0 = <&pwm10m1_pins &pwm10m2_pins>;
};
&pwm11 {
pinctrl-0 = <&pwm11m1_pins &pwm11m2_pins>;
};
&pinctrl {
spi0 {
spi0m0_clk: spi0m0-clk {
rockchip,pins = <1 RK_PC1 4 &pcfg_pull_none>;
};
spi0m0_mosi: spi0m0-mosi {
rockchip,pins = <1 RK_PC2 6 &pcfg_pull_none>;
};
spi0m0_miso: spi0m0-miso {
rockchip,pins = <1 RK_PC3 6 &pcfg_pull_none>;
};
spi0m0_cs0: spi0m0-cs0 {
rockchip,pins = <1 RK_PC0 4 &pcfg_pull_none>;
};
};
};

1
sysdrv/source/kernel/arch/arm/boot/dts/rv1106.dtsi
View File

@@ -359,6 +359,7 @@
mode-ums = <BOOT_UMS>;
mode-panic = <BOOT_PANIC>;
mode-watchdog = <BOOT_WATCHDOG>;
mode-uboot = <BOOT_TO_UBOOT>;
};
rgb: rgb {

148
sysdrv/source/kernel/arch/arm/boot/dts/rv1106g-luckfox-pico-pro-max.dts
View File

@@ -14,8 +14,6 @@
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1106";
};
/**********FLASH**********/
&sfc {
status = "okay";
@@ -43,20 +41,6 @@
status = "okay";
};
/**********SDIO**********/
// &sdio {
// max-frequency = <50000000>;
// no-sdio;
// no-mmc;
// bus-width = <4>;
// cap-mmc-highspeed;
// cap-sd-highspeed;
// disable-wp;
// pinctrl-names = "default";
// pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4 &clk_32k>;
// status = "okay";
// };
/**********ETH**********/
&gmac {
status = "okay";
@@ -68,25 +52,9 @@
dr_mode = "peripheral";
};
/**********I2C**********/
// &i2c1 {
// status = "okay";
// pinctrl-0 = <&i2c1m1_xfer>;
// clock-frequency = <100000>;
// };
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3m1_xfer>;
clock-frequency = <100000>;
};
// /**********SPI**********/
/**********SPI**********/
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
cs-gpios = <&gpio1 RK_PC0 1>;
// cs-gpios = <&gpio1 26 1>;
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
@@ -96,110 +64,38 @@
};
};
/**********I2C**********/
/* I2C3_M1 */
&i2c3 {
status = "disabled";
clock-frequency = <100000>;
};
/* I2C1_M1 */
&i2c1 {
status = "disabled";
clock-frequency = <100000>;
};
/**********UART**********/
// &uart0 {
// status = "okay";
// pinctrl-names = "default";
// pinctrl-0 = <&uart0m1_xfer>;
// };
// &uart1 {
// status = "okay";
// pinctrl-names = "default";
// pinctrl-0 = <&uart1m1_xfer>;
// };
/* UART3_M1 */
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>;
status = "disabled";
};
/* UART4_M1 */
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4m1_xfer>;
status = "disabled";
};
// /**********PWM**********/
// &pwm0 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm0m0_pins>;
// // pinctrl-0 = <&pwm0m1_pins>;
// };
// &pwm1 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm1m0_pins>;
// // pinctrl-0 = <&pwm1m1_pins>;
// };
//&pwm2 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm2m2_pins>;
//};
//&pwm3 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm3m2_pins>;
//};
//&pwm4 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm4m2_pins>;
//};
&pwm5 {
/**********PWM**********/
/* PWM5_M1 */
&pwm1 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm5m1_pins>;
// pinctrl-0 = <&pwm5m2_pins>;
};
&pwm6 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm6m1_pins>;
// pinctrl-0 = <&pwm6m2_pins>;
};
//&pwm7 {
// status = "okay";
// pinctrl-names = "active";
// pinctrl-0 = <&pwm7m2_pins>;
//};
//&pwm8 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm8m1_pins>;
// pinctrl-0 = <&pwm8m0_pins>;
//};
//&pwm9 {
// status = "okay";
// pinctrl-names = "active";
// // pinctrl-0 = <&pwm9m1_pins>;
// pinctrl-0 = <&pwm9m0_pins>;
//};
&pwm10 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm10m1_pins>;
// pinctrl-0 = <&pwm10m2_pins>;
// pinctrl-0 = <&pwm10m0_pins>;
};
&pwm11 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm11m1_pins>;
// pinctrl-0 = <&pwm11m2_pins>;
// pinctrl-0 = <&pwm11m0_pins>;
};
/**********RTC**********/
&rtc {
status = "okay";
};

116
sysdrv/source/kernel/arch/arm/boot/dts/rv1106g-luckfox-pico-ultra-w.dts Executable file
View File

@@ -0,0 +1,116 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-luckfox-pico-ultra-ipc.dtsi"
#include "rv1106-thunder-boot-emmc.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/display/media-bus-format.h>
/ {
model = "Luckfox Pico Ultra W";
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1106";
restart-poweroff {
compatible = "restart-poweroff";
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
};
};
/**********EMMC**********/
&emmc {
memory-region-ecsd = <&mmc_ecsd>;
post-power-on-delay-ms = <0>;
status = "okay";
};
&fiq_debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";
};
/**********SDIO-WIFI**********/
&sdmmc {
max-frequency = <50000000>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
// no-sd;
// no-mmc;
supports-sdio;
mmc-pwrseq = <&sdio_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
status = "okay";
};
&pinctrl{
sdmmc0{
sdmmc0_det: sdmmc0-det {
rockchip,pins =
/* sdmmc0_det */
<3 RK_PA1 1 &pcfg_pull_down>;
};
};
};
/**********ETH**********/
&gmac {
status = "okay";
};
/**********USB**********/
&usbdrd_dwc3 {
status = "okay";
dr_mode = "peripheral";
#dr_mode = "host";
};
/**********RTC**********/
&rtc {
status = "okay";
};
/**********BT**********/
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
};
&pinctrl {
uart1 {
uart1m0_ctsn: uart1m0-ctsn{
rockchip,pins = <0 RK_PA6 2 &pcfg_pull_down>;
};
uart1m0_rtsn: uart1m0-rtsn{
rockchip,pins = <0 RK_PA5 2 &pcfg_pull_down>;
};
};
};
/**********TP**********/
&i2c3 {
status = "disabled";
};
/**********SPI**********/
&spi0 {
status = "disabled";
spidev@0 {
spi-max-frequency = <50000000>;
};
};

67
sysdrv/source/kernel/arch/arm/boot/dts/rv1106g-luckfox-pico-ultra.dts Executable file
View File

@@ -0,0 +1,67 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-luckfox-pico-ultra-ipc.dtsi"
#include "rv1106-thunder-boot-emmc.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/display/media-bus-format.h>
/ {
model = "Luckfox Pico Ultra";
compatible = "rockchip,rv1103g-38x38-ipc-v10", "rockchip,rv1106";
restart-poweroff {
compatible = "restart-poweroff";
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
};
};
/**********EMMC**********/
&emmc {
memory-region-ecsd = <&mmc_ecsd>;
post-power-on-delay-ms = <0>;
status = "okay";
};
&fiq_debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";
};
/**********ETH**********/
&gmac {
status = "okay";
};
/**********USB**********/
&usbdrd_dwc3 {
status = "okay";
dr_mode = "peripheral";
};
/**********RTC**********/
&rtc {
status = "okay";
};
/**********TP**********/
&i2c3 {
status = "disabled";
};
/**********SPI**********/
&spi0 {
status = "disabled";
spidev@0 {
spi-max-frequency = <50000000>;
};
};

25
sysdrv/source/kernel/arch/arm/configs/luckfox_rv1106_linux_defconfig
View File

@@ -68,8 +68,13 @@ CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_MISC=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_DTBO=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_UFSHCD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CORE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
@@ -136,7 +141,11 @@ CONFIG_WIFI_BUILD_MODULE=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_GOODIX=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
@@ -166,7 +175,6 @@ CONFIG_THERMAL=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
@@ -180,6 +188,8 @@ CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
# CONFIG_MEDIA_TEST_SUPPORT is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=y
CONFIG_VIDEOBUF2_CMA_SG=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ROCKCHIP_CIF=m
@@ -199,7 +209,6 @@ CONFIG_DRM_SII902X=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_ROCKCHIP_MULTI_RGA=m
CONFIG_ROCKCHIP_RGA_PROC_FS=y
# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set
CONFIG_ROCKCHIP_RVE=m
CONFIG_ROCKCHIP_RVE_PROC_FS=y
CONFIG_ROCKCHIP_DVBM=m
@@ -219,17 +228,23 @@ CONFIG_SND_SIMPLE_CARD=y
# CONFIG_HID is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_GADGETFS=y
CONFIG_USB_MASS_STORAGE=y
CONFIG_MMC=y
# CONFIG_PWRSEQ_EMMC is not set
CONFIG_MMC_BLOCK_MINORS=32
@@ -267,16 +282,13 @@ CONFIG_COMMON_CLK_PROCFS=y
CONFIG_CPU_RV1106=y
CONFIG_ROCKCHIP_AMP=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_OPP=y
CONFIG_ROCKCHIP_IOMUX=y
CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_RK_MEMBLOCK_PROCFS=y
CONFIG_PM_DEVFREQ=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_ROCKCHIP_SARADC=y
@@ -288,7 +300,6 @@ CONFIG_PHY_ROCKCHIP_MIPI_RX=y
CONFIG_ANDROID=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_ROCKCHIP_RKNPU=m
# CONFIG_ROCKCHIP_RKNPU_DEBUG_FS is not set
CONFIG_ROCKCHIP_RKNPU_PROC_FS=y
CONFIG_ROCKCHIP_RKNPU_DMA_HEAP=y
CONFIG_EXT4_FS=y

346
sysdrv/source/kernel/arch/arm/configs/luckfox_rv1106_linux_w_defconfig Executable file
View File

@@ -0,0 +1,346 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_XZ=y
CONFIG_DEFAULT_HOSTNAME="localhost"
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_BUG is not set
# CONFIG_BASE_FULL is not set
# CONFIG_IO_URING is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_ARCH_ROCKCHIP=y
# CONFIG_VDSO is not set
CONFIG_VMSPLIT_3G_OPT=y
CONFIG_HZ_300=y
CONFIG_THUMB2_KERNEL=y
# CONFIG_CPU_SW_DOMAIN_PAN is not set
CONFIG_FORCE_MAX_ZONEORDER=9
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_CMDLINE="user_debug=31"
CONFIG_CMDLINE_EXTEND=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPUFREQ_DT=y
CONFIG_ARM_ROCKCHIP_CPUFREQ=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_SUSPEND is not set
CONFIG_JUMP_LABEL=y
# CONFIG_STACKPROTECTOR_STRONG is not set
# CONFIG_STRICT_KERNEL_RWX is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_EFI_PARTITION is not set
CONFIG_CMDLINE_PARTITION=y
# CONFIG_MQ_IOSCHED_KYBER is not set
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_CMA=y
CONFIG_CMA_INACTIVE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=m
# CONFIG_IPV6_SIT is not set
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_RFKILL=y
CONFIG_RFKILL_RK=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_OF_PARTS is not set
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
CONFIG_MTD_SPI_NOR_MISC=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_UFSHCD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CORE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_AURORA is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_STMMAC_ETH=y
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
CONFIG_RK630_PHY=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_WL_ROCKCHIP=m
CONFIG_WIFI_BUILD_MODULE=y
# CONFIG_BCMDHD is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_NR_UARTS=6
CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_SERIAL_8250_DW=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_ROCKCHIP=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_RK3X=y
CONFIG_SPI=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_SFC=y
CONFIG_SPI_SPIDEV=y
CONFIG_SPI_SLAVE=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_POWER_SUPPLY=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
# CONFIG_MEDIA_CEC_SUPPORT is not set
CONFIG_MEDIA_SUPPORT=y
# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
# CONFIG_MEDIA_RADIO_SUPPORT is not set
# CONFIG_MEDIA_SDR_SUPPORT is not set
# CONFIG_MEDIA_TEST_SUPPORT is not set
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=y
CONFIG_VIDEOBUF2_CMA_SG=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ROCKCHIP_CIF=m
CONFIG_VIDEO_ROCKCHIP_ISP=m
CONFIG_VIDEO_RK_IRCUT=y
CONFIG_VIDEO_OS04A10=m
CONFIG_VIDEO_SC3336=m
CONFIG_VIDEO_SC4336=m
CONFIG_VIDEO_SC530AI=m
CONFIG_DRM=y
CONFIG_DRM_EDID=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_RGB=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_SII902X=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_ROCKCHIP_MULTI_RGA=m
CONFIG_ROCKCHIP_RGA_PROC_FS=y
# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set
CONFIG_ROCKCHIP_RVE=m
CONFIG_ROCKCHIP_RVE_PROC_FS=y
CONFIG_ROCKCHIP_DVBM=m
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_PCM_TIMER is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_PROC_FS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
CONFIG_SND_SOC_RV1106=y
CONFIG_SND_SIMPLE_CARD=y
# CONFIG_HID is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_CONFIGFS_RNDIS=y
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_UAC1=y
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_MASS_STORAGE=y
CONFIG_MMC=y
# CONFIG_PWRSEQ_EMMC is not set
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_QUEUE_DEPTH=1
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_ROCKCHIP=y
CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y
CONFIG_DMABUF_HEAPS_ROCKCHIP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_ALIGNMENT=0
CONFIG_DMABUF_RK_HEAPS_DEBUG=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set
CONFIG_STAGING=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_FIQ_DEBUGGER_FIQ_GLUE=y
CONFIG_FB_TFT=y
CONFIG_FB_TFT_ST7735R=y
CONFIG_FB_TFT_ST7789V=y
CONFIG_COMMON_CLK_PROCFS=y
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_CPU_RV1106=y
CONFIG_ROCKCHIP_AMP=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_OPP=y
CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_RK_MEMBLOCK_PROCFS=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_ROCKCHIP_SARADC=y
CONFIG_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_MIPI_RX=y
CONFIG_ANDROID=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_ROCKCHIP_RKNPU=m
# CONFIG_ROCKCHIP_RKNPU_DEBUG_FS is not set
CONFIG_ROCKCHIP_RKNPU_PROC_FS=y
CONFIG_ROCKCHIP_RKNPU_DMA_HEAP=y
CONFIG_EXT4_FS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
# CONFIG_DNOTIFY is not set
CONFIG_VFAT_FS=y
CONFIG_EXFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
# CONFIG_JFFS2_RTIME is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_ZSTD is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_ZLIB is not set
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_CRYPTO_ZSTD=y
# CONFIG_CRYPTO_HW is not set
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
# CONFIG_XZ_DEC_SPARC is not set
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=0
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=8
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_MISC is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set

7
sysdrv/source/kernel/arch/arm/configs/rv1106-bt.config Normal file
View File

@@ -0,0 +1,7 @@
CONFIG_BT=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_RFKILL=y
CONFIG_RFKILL_RK=y

6
sysdrv/source/kernel/arch/arm/configs/rv1106-pm.config Normal file
View File

@@ -0,0 +1,6 @@
CONFIG_PM_DEBUG=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_PM_WAKELOCKS=y
CONFIG_SUSPEND=y
CONFIG_ROCKCHIP_SUSPEND_MODE=y

12
sysdrv/source/kernel/arch/arm/configs/rv1106-usb.config Normal file
View File

@@ -0,0 +1,12 @@
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_UFSHCD=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_MASS_STORAGE=y
CONFIG_DEBUG_FS=y

5
sysdrv/source/kernel/drivers/input/touchscreen/Kconfig
View File

@@ -425,6 +425,11 @@ config TOUCHSCREEN_GSLX680_PAD
config TOUCHSCREEN_GT1X
tristate "GT1X touchscreens support"
config TOUCHSCREEN_GT9XX
tristate "GT9XX touchscreens support"
config TOUCHSCREEN_HIDEEP
tristate "HiDeep Touch IC"
depends on I2C

1
sysdrv/source/kernel/drivers/input/touchscreen/Makefile
View File

@@ -52,6 +52,7 @@ gsl3673-ts-y := gsl3673.o gsl_point_id.o
obj-$(CONFIG_TOUCHSCREEN_GSLX680_PAD) += gslx680-pad.o
gslx680-pad-y := gslx680_pad.o gsl_point_id.o
obj-$(CONFIG_TOUCHSCREEN_GT1X) += gt1x/
obj-$(CONFIG_TOUCHSCREEN_GT9XX) += gt9xx/
obj-$(CONFIG_TOUCHSCREEN_HIDEEP) += hideep.o
obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o
obj-$(CONFIG_TOUCHSCREEN_IMX6UL_TSC) += imx6ul_tsc.o

25
sysdrv/source/kernel/drivers/input/touchscreen/edt-ft5x06.c
View File

@@ -12,7 +12,7 @@
* Development of this driver has been sponsored by Glyn:
* http://www.glyn.com/Products/Displays
*/
#define DEBUG
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
@@ -832,8 +832,10 @@ static int edt_ft5x06_ts_identify(struct i2c_client *client,
error = edt_ft5x06_ts_readwrite(client, 1, "\xBB",
EDT_NAME_LEN - 1, rdbuf);
if (error)
return error;
{
dev_dbg(&client->dev, "edt_ft5x06_ts_read_write xBB failed\n");
//return error;
}
/* Probe content for something consistent.
* M06 starts with a response byte, M12 gives the data directly.
* M09/Generic does not provide model number information.
@@ -881,15 +883,19 @@ static int edt_ft5x06_ts_identify(struct i2c_client *client,
error = edt_ft5x06_ts_readwrite(client, 1, "\xA6",
2, rdbuf);
if (error)
{
dev_dbg(&client->dev, "edt_ft5x06_ts_read_write XA6 failed\n");
return error;
}
strlcpy(fw_version, rdbuf, 2);
error = edt_ft5x06_ts_readwrite(client, 1, "\xA8",
1, rdbuf);
if (error)
{
dev_dbg(&client->dev, "edt_ft5x06_ts_read_write xA8 failed\n");
return error;
}
/* This "model identification" is not exact. Unfortunately
* not all firmwares for the ft5x06 put useful values in
* the identification registers.
@@ -917,7 +923,10 @@ static int edt_ft5x06_ts_identify(struct i2c_client *client,
error = edt_ft5x06_ts_readwrite(client, 1, "\x53",
1, rdbuf);
if (error)
{
dev_dbg(&client->dev, "edt_ft5x06_ts_read_write x53 failed\n");
return error;
}
strlcpy(fw_version, rdbuf, 1);
snprintf(model_name, EDT_NAME_LEN,
"EVERVISION-FT5726NEi");
@@ -1155,7 +1164,8 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
}
if (tsdata->reset_gpio) {
usleep_range(5000, 6000);
//usleep_range(5000, 6000);
usleep_range(6000, 7000);
gpiod_set_value_cansleep(tsdata->reset_gpio, 0);
msleep(300);
}
@@ -1174,7 +1184,8 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
error = edt_ft5x06_ts_identify(client, tsdata, fw_version);
if (error) {
dev_err(&client->dev, "touchscreen probe failed\n");
return error;
dev_err(&client->dev, "error = %d\n",error);
// return error;
}
/*

22
sysdrv/source/kernel/drivers/input/touchscreen/goodix.c
View File

@@ -10,6 +10,7 @@
* 2010 - 2012 Goodix Technology.
*/
#define DEBUG
#include <linux/kernel.h>
#include <linux/dmi.h>
@@ -962,6 +963,8 @@ static int goodix_read_version(struct goodix_ts_data *ts)
{
int error;
u8 buf[6];
//u8 reg_data[6];
//int i = 0;
char id_str[GOODIX_ID_MAX_LEN + 1];
error = goodix_i2c_read(ts->client, GOODIX_REG_ID, buf, sizeof(buf));
@@ -978,7 +981,6 @@ static int goodix_read_version(struct goodix_ts_data *ts)
dev_info(&ts->client->dev, "ID %s, version: %04x\n", ts->id,
ts->version);
return 0;
}
@@ -1058,11 +1060,15 @@ static int goodix_configure_dev(struct goodix_ts_data *ts)
input_set_abs_params(ts->input_dev, ABS_MT_WIDTH_MAJOR, 0, 255, 0, 0);
input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
dev_dbg(&ts->client->dev, "(%d, %d, %d)", ts->prop.max_x, ts->prop.max_y, ts->max_touch_num);
/* Read configuration and apply touchscreen parameters */
goodix_read_config(ts);
dev_dbg(&ts->client->dev, "(%d, %d, %d)", ts->prop.max_x, ts->prop.max_y, ts->max_touch_num);
/* Try overriding touchscreen parameters via device properties */
touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
dev_dbg(&ts->client->dev, "(%d, %d, %d)", ts->prop.max_x, ts->prop.max_y, ts->max_touch_num);
if (!ts->prop.max_x || !ts->prop.max_y || !ts->max_touch_num) {
dev_err(&ts->client->dev,
@@ -1127,9 +1133,17 @@ static void goodix_config_cb(const struct firmware *cfg, void *ctx)
{
struct goodix_ts_data *ts = ctx;
int error;
int i;
if (cfg) {
/* send device configuration to the firmware */
while(i < cfg->size)
{
dev_dbg(&ts->client->dev, "reg %d: %#x\n", i, cfg->data[i]);
i ++;
}
error = goodix_send_cfg(ts, cfg->data, cfg->size);
if (error)
goto err_release_cfg;
@@ -1229,8 +1243,11 @@ reset:
ts->chip = goodix_get_chip_data(ts->id);
ts->load_cfg_from_disk = 0;
if (ts->load_cfg_from_disk) {
/* update device config */
dev_dbg(&client->dev, "Configure from Disk\n");
ts->cfg_name = devm_kasprintf(&client->dev, GFP_KERNEL,
"goodix_%s_cfg.bin", ts->id);
if (!ts->cfg_name)
@@ -1248,6 +1265,7 @@ reset:
return 0;
} else {
dev_dbg(&client->dev, "Configure from Device\n");
error = goodix_configure_dev(ts);
if (error)
return error;

2
sysdrv/source/kernel/drivers/input/touchscreen/gt9xx/Makefile
View File

@@ -3,4 +3,4 @@ obj-y += goodix_gt9xx.o
#goodix_gt9xx-y +=goodix_tool.o
goodix_gt9xx-y +=gt9xx.o
goodix_gt9xx-y +=gt9xx_update.o
#goodix_gt9xx-y +=gt9xx_update.o

31
sysdrv/source/kernel/drivers/input/touchscreen/gt9xx/gt9xx.h
View File

@@ -218,6 +218,7 @@ extern u16 total_len;
}
*/
/*
//WGJ10187_GT9271_Config_20140623_104014_0X41.cfg
#define CTP_CFG_GROUP1 {\
0x41,0x80,0x07,0xB0,0x04,0x0A,0x05,0x00,0x01,0x08,0x28,0x0F,0x50,0x32,0x03, \
@@ -234,6 +235,32 @@ extern u16 total_len;
0x23,0x24,0x25,0x26,0x27,0x28,0x29,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x00,0xB5,0x01 \
}
*/
//FT040017_GT911_Config_20221026.cfg
#define CTP_CFG_GROUP1 { \
0x4F,0xE0,0x01,0xE0,0x01,0x05,0x35,0x00,0x01,0xC8, \
0x28,0x0F,0x50,0x3C,0x03,0x05,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x18,0x1A,0x1E,0x14,0x85,0x25,0x0A, \
0xEA,0xEC,0xB5,0x06,0x00,0x00,0x00,0x20,0x21,0x10, \
0x00,0x01,0x00,0x0F,0x00,0x2A,0x00,0x00,0x01,0x50, \
0x32,0xDC,0xFA,0x94,0xD0,0x02,0x08,0x00,0x00,0x04, \
0x80,0xDE,0x00,0x80,0xE4,0x00,0x80,0xEA,0x00,0x7F, \
0xF0,0x00,0x7F,0xF6,0x00,0x7F,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x14,0x12,0x10,0x0E,0x0C,0x0A,0x08,0x06, \
0x04,0x02,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, \
0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, \
0xFF,0xFF,0x21,0x20,0x1F,0x1E,0x1D,0x00,0x02,0x04, \
0x06,0x08,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, \
0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, \
0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, \
0xFF,0xFF,0xFF,0xFF,0xAA,0x01 \
}
// TODO: define your config for Sensor_ID == 1 here, if needed
#define CTP_CFG_GROUP2 {\
@@ -391,7 +418,7 @@ extern u16 total_len;
}while (0)
//*****************************End of Part III********************************
#define TRUE 1
#define FALSE 0
//#define TRUE 1
//#define FALSE 0
#endif /* _GOODIX_GT9XX_H_ */

1
sysdrv/source/kernel/drivers/mmc/Makefile
View File

@@ -2,6 +2,7 @@
#
# Makefile for the kernel mmc device drivers.
#
#subdir-ccflags-y := -DDEBUG
obj-$(CONFIG_MMC) += core/
obj-$(subst m,y,$(CONFIG_MMC)) += host/

7
sysdrv/source/kernel/drivers/of/Kconfig
View File

@@ -121,4 +121,11 @@ config OF_DMA_DEFAULT_COHERENT
# arches should select this if DMA is coherent by default for OF devices
bool
config OF_DTBO
bool "Device Tree DTBO"
select OF_DYNAMIC
select OF_FLATTREE
select OF_RESOLVE
help
Device Tree DTBO
endif # OF

1
sysdrv/source/kernel/drivers/of/Makefile
View File

@@ -13,5 +13,6 @@ obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
obj-$(CONFIG_OF_RESOLVE) += resolver.o
obj-$(CONFIG_OF_OVERLAY) += overlay.o
obj-$(CONFIG_OF_NUMA) += of_numa.o
obj-$(CONFIG_OF_DTBO) += dtbocfg.o
obj-$(CONFIG_OF_UNITTEST) += unittest-data/

429
sysdrv/source/kernel/drivers/of/dtbocfg.c Normal file
View File

@@ -0,0 +1,429 @@
/*********************************************************************************
*
* Copyright (C) 2016-2023 Ichiro Kawazome
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/configfs.h>
#include <linux/types.h>
#include <linux/stat.h>
#include <linux/limits.h>
#include <linux/file.h>
#include <linux/version.h>
#define DRIVER_NAME "dtbocfg"
#define DRIVER_VERSION "0.1.0"
/**
* Device Tree Overlay Item Structure
*/
struct dtbocfg_overlay_item {
struct config_item item;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))
struct device_node* node;
#endif
int id;
void* dtbo;
int dtbo_size;
};
/**
* dtbocfg_overlay_create() - Create Device Tree Overlay
* @overlay: Pointer to Device Tree Overlay Item
* return Success(0) or Error Status.
*/
static int dtbocfg_overlay_item_create(struct dtbocfg_overlay_item *overlay)
{
int ret_val;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 17, 0))
{
int ovcs_id = 0;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0))
ret_val = of_overlay_fdt_apply(overlay->dtbo,overlay->dtbo_size, &ovcs_id, NULL);
#else
ret_val = of_overlay_fdt_apply(overlay->dtbo,overlay->dtbo_size, &ovcs_id);
#endif
if (ret_val != 0) {
pr_err("%s: Failed to apply overlay (ret_val=%d)\n", __func__, ret_val);
goto failed;
}
overlay->id = ovcs_id;
pr_debug("%s: apply OK(id=%d)\n", __func__, ovcs_id);
}
#else
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
of_fdt_unflatten_tree(overlay->dtbo, NULL, &overlay->node);
#else
of_fdt_unflatten_tree(overlay->dtbo, &overlay->node);
#endif
if (overlay->node == NULL) {
pr_err("%s: failed to unflatten tree\n", __func__);
ret_val = -EINVAL;
goto failed;
}
pr_debug("%s: unflattened OK\n", __func__);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
{
int ovcs_id = 0;
ret_val = of_overlay_apply(overlay->node, &ovcs_id);
if (ret_val != 0) {
pr_err("%s: Failed to apply overlay (ret_val=%d)\n", __func__, ret_val);
goto failed;
}
overlay->id = ovcs_id;
pr_debug("%s: apply OK(id=%d)\n", __func__, ovcs_id);
}
#else
{
of_node_set_flag(overlay->node, OF_DETACHED);
ret_val = of_resolve_phandles(overlay->node);
if (ret_val != 0) {
pr_err("%s: Failed to resolve tree\n", __func__);
goto failed;
}
pr_debug("%s: resolved OK\n", __func__);
ret_val = of_overlay_create(overlay->node);
if (ret_val < 0) {
pr_err("%s: Failed to create overlay (ret_val=%d)\n", __func__, ret_val);
goto failed;
}
overlay->id = ret_val;
}
#endif
#endif
pr_debug("%s: create OK\n", __func__);
return 0;
failed:
return ret_val;
}
/**
* dtbocfg_overlay_item_release() - Relase Device Tree Overlay
* @overlay: Pointer to Device Tree Overlay Item
* return none
*/
static void dtbocfg_overlay_item_release(struct dtbocfg_overlay_item *overlay)
{
if (overlay->id >= 0) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
of_overlay_remove(&overlay->id);
#else
of_overlay_destroy(overlay->id);
#endif
overlay->id = -1;
}
}
/**
* container_of_dtbocfg_overlay_item() - Get Device Tree Overlay Item Pointer from Configuration Item
* @item: Pointer to Configuration Item
* return Pointer to Device Tree Overlay Item
*/
static inline struct dtbocfg_overlay_item* container_of_dtbocfg_overlay_item(struct config_item *item)
{
return item ? container_of(item, struct dtbocfg_overlay_item, item) : NULL;
}
/**
* dtbocfg_overlay_item_status_store() - Set Status Attibute
* @item: Pointer to Configuration Item
* @page: Pointer to Value Buffer
* @count: Size of Value Buffer Size
* return Stored Size or Error Status.
*/
static ssize_t dtbocfg_overlay_item_status_store(struct config_item *item, const char *buf, size_t count)
{
struct dtbocfg_overlay_item *overlay = container_of_dtbocfg_overlay_item(item);
ssize_t status;
unsigned long value;
if (0 != (status = kstrtoul(buf, 10, &value))) {
goto failed;
}
if (value == 0) {
if (overlay->id >= 0) {
dtbocfg_overlay_item_release(overlay);
}
} else {
if (overlay->id < 0) {
dtbocfg_overlay_item_create(overlay);
}
}
return count;
failed:
return -EPERM;
}
/**
* dtbocfg_overlay_item_status_show() - Show Status Attibute
* @item : Pointer to Configuration Item
* @page : Pointer to Value for Store
* return String Size or Error Status.
*/
static ssize_t dtbocfg_overlay_item_status_show(struct config_item *item, char *page)
{
struct dtbocfg_overlay_item *overlay = container_of_dtbocfg_overlay_item(item);
return sprintf(page, "%d\n", overlay->id >= 0 ? 1 : 0);
}
/**
* dtbocfg_overlay_item_dtbo_write() - Write Device Tree Blob to Configuration Item
* @item : Pointer to Configuration Item
* @page : Pointer to Value Buffer
* @count: Size of Value Buffer
* return Stored Size or Error Status.
*/
static ssize_t dtbocfg_overlay_item_dtbo_write(struct config_item *item, const void *buf, size_t count)
{
struct dtbocfg_overlay_item *overlay = container_of_dtbocfg_overlay_item(item);
if (overlay->dtbo_size > 0) {
if (overlay->id >= 0) {
return -EPERM;
}
kfree(overlay->dtbo);
overlay->dtbo = NULL;
overlay->dtbo_size = 0;
}
overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
if (overlay->dtbo == NULL) {
overlay->dtbo_size = 0;
return -ENOMEM;
} else {
overlay->dtbo_size = count;
return count;
}
}
/**
* dtbocfg_overlay_item_dtbo_read() - Read Device Tree Blob from Configuration Item
* @item : Pointer to Configuration Item
* @page : Pointer to Value for Store, or NULL to query the buffer size
* @size : Size of the supplied buffer
* return Read Size
*/
static ssize_t dtbocfg_overlay_item_dtbo_read(struct config_item *item, void *buf, size_t size)
{
struct dtbocfg_overlay_item *overlay = container_of_dtbocfg_overlay_item(item);
if (overlay->dtbo == NULL)
return 0;
if (buf != NULL)
memcpy(buf, overlay->dtbo, overlay->dtbo_size);
return overlay->dtbo_size;
}
/**
* Device Tree Blob Overlay Attribute Structure
*/
CONFIGFS_BIN_ATTR(dtbocfg_overlay_item_, dtbo, NULL, 1024 * 1024); // 1MiB should be way more than enough
CONFIGFS_ATTR(dtbocfg_overlay_item_, status);
static struct configfs_attribute *dtbocfg_overlay_attrs[] = {
&dtbocfg_overlay_item_attr_status,
NULL,
};
static struct configfs_bin_attribute *dtbocfg_overlay_bin_attrs[] = {
&dtbocfg_overlay_item_attr_dtbo,
NULL,
};
/**
* dtbocfg_overlay_release() - Release Device Tree Overlay Item
* @item : Pointer to Configuration Item
* Return None
*/
static void dtbocfg_overlay_release(struct config_item *item)
{
struct dtbocfg_overlay_item *overlay = container_of_dtbocfg_overlay_item(item);
pr_debug("%s\n", __func__);
dtbocfg_overlay_item_release(overlay);
if (overlay->dtbo) {
kfree(overlay->dtbo);
overlay->dtbo = NULL;
overlay->dtbo_size = 0;
}
kfree(overlay);
}
/**
* Device Tree Blob Overlay Item Structure
*/
static struct configfs_item_operations dtbocfg_overlay_item_ops = {
.release = dtbocfg_overlay_release,
};
static struct config_item_type dtbocfg_overlay_item_type = {
.ct_item_ops = &dtbocfg_overlay_item_ops,
.ct_attrs = dtbocfg_overlay_attrs,
.ct_bin_attrs = dtbocfg_overlay_bin_attrs,
.ct_owner = THIS_MODULE,
};
/**
* dtbocfg_overlay_group_make_item() - Make Device Tree Overlay Group Item
* @group: Pointer to Configuration Group
* @name : Pointer to Group Name
* Return Pointer to Device Tree Overlay Group Item
*/
static struct config_item *dtbocfg_overlay_group_make_item(struct config_group *group, const char *name)
{
struct dtbocfg_overlay_item *overlay;
pr_debug("%s\n", __func__);
overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
if (!overlay)
return ERR_PTR(-ENOMEM);
overlay->id = -1;
overlay->dtbo = NULL;
overlay->dtbo_size = 0;
config_item_init_type_name(&overlay->item, name, &dtbocfg_overlay_item_type);
return &overlay->item;
}
/**
* dtbocfg_overlay_group_drop_item() - Drop Device Tree Overlay Group Item
* @group: Pointer to Configuration Group
* @item : Pointer to Device Tree Overlay Group Item
*/
static void dtbocfg_overlay_group_drop_item(struct config_group *group, struct config_item *item)
{
struct dtbocfg_overlay_item *overlay = container_of_dtbocfg_overlay_item(item);
pr_debug("%s\n", __func__);
config_item_put(&overlay->item);
}
/**
* Device Tree Blob Overlay Sub Group Structures
*/
static struct configfs_group_operations dtbocfg_overlays_ops = {
.make_item = dtbocfg_overlay_group_make_item,
.drop_item = dtbocfg_overlay_group_drop_item,
};
static struct config_item_type dtbocfg_overlays_type = {
.ct_group_ops = &dtbocfg_overlays_ops,
.ct_owner = THIS_MODULE,
};
static struct config_group dtbocfg_overlay_group;
/**
* Device Tree Blob Overlay Root Sub System Structures
*/
static struct configfs_group_operations dtbocfg_root_ops = {
/* empty - we don't allow anything to be created */
};
static struct config_item_type dtbocfg_root_type = {
.ct_group_ops = &dtbocfg_root_ops,
.ct_owner = THIS_MODULE,
};
static struct configfs_subsystem dtbocfg_root_subsys = {
.su_group = {
.cg_item = {
.ci_namebuf = "device-tree",
.ci_type = &dtbocfg_root_type,
},
},
.su_mutex = __MUTEX_INITIALIZER(dtbocfg_root_subsys.su_mutex),
};
/**
* dtbocfg_module_init()
*/
static int __init dtbocfg_module_init(void)
{
int retval = 0;
pr_info(DRIVER_NAME ": " DRIVER_VERSION "\n");
config_group_init(&dtbocfg_root_subsys.su_group);
config_group_init_type_name(&dtbocfg_overlay_group, "overlays", &dtbocfg_overlays_type);
retval = configfs_register_subsystem(&dtbocfg_root_subsys);
if (retval != 0) {
pr_err( "%s: couldn't register subsys\n", __func__);
goto register_subsystem_failed;
}
retval = configfs_register_group(&dtbocfg_root_subsys.su_group, &dtbocfg_overlay_group);
if (retval != 0) {
pr_err( "%s: couldn't register group\n", __func__);
goto register_group_failed;
}
pr_info(DRIVER_NAME ": OK\n");
return 0;
register_group_failed:
configfs_unregister_subsystem(&dtbocfg_root_subsys);
register_subsystem_failed:
return retval;
}
/**
* dtbocfg_module_exit()
*/
static void __exit dtbocfg_module_exit(void)
{
configfs_unregister_group(&dtbocfg_overlay_group);
configfs_unregister_subsystem(&dtbocfg_root_subsys);
}
module_init(dtbocfg_module_init);
module_exit(dtbocfg_module_exit);
MODULE_AUTHOR("ikwzm");
MODULE_DESCRIPTION("Device Tree Overlay Configuration File System");
MODULE_LICENSE("Dual BSD/GPL");

4
sysdrv/source/kernel/include/dt-bindings/soc/rockchip,boot-mode.h
View File

@@ -20,5 +20,9 @@
#define BOOT_CHARGING (REBOOT_FLAG + 11)
/* enter usb mass storage mode */
#define BOOT_UMS (REBOOT_FLAG + 12)
/* enter reboot to uboot */
#define BOOT_TO_UBOOT (REBOOT_FLAG + 14)
#endif

BIN
sysdrv/source/kernel/tools/testing/selftests/rkpinctrl/iomux Executable file
View File

Binary file not shown.

2
sysdrv/source/uboot/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h
View File

@@ -26,6 +26,8 @@
/* enter bootrom download mode */
#define BOOT_BROM_DOWNLOAD 0xEF08A53C
#define BOOT_TO_UBOOT (REBOOT_FLAG + 14)
#ifndef __ASSEMBLY__
int setup_boot_mode(void);
#endif

11
sysdrv/source/uboot/u-boot/arch/arm/mach-rockchip/boot_mode.c
View File

@@ -189,6 +189,11 @@ int rockchip_get_boot_mode(void)
boot_mode[PL] = BOOT_MODE_UMS;
clear_boot_reg = 1;
break;
case BOOT_TO_UBOOT:
printf("boot mode: uboot\n");
boot_mode[PL] = BOOT_MODE_UBOOT_TERMINAL;
clear_boot_reg = 1;
break;
case BOOT_CHARGING:
printf("boot mode: charging\n");
boot_mode[PL] = BOOT_MODE_CHARGING;
@@ -227,6 +232,8 @@ int setup_boot_mode(void)
{
char env_preboot[256] = {0};
env_set("cli", NULL); /* removed by default */
switch (rockchip_get_boot_mode()) {
case BOOT_MODE_BOOTLOADER:
printf("enter fastboot!\n");
@@ -259,6 +266,10 @@ int setup_boot_mode(void)
printf("enter charging!\n");
env_set("preboot", "setenv preboot; charge");
break;
case BOOT_MODE_UBOOT_TERMINAL:
printf("enter uboot!\n");
env_set("cli", "yes");
break;
}
return 0;

2
sysdrv/source/uboot/u-boot/common/autoboot.c
View File

@@ -220,7 +220,7 @@ static int __abortboot(int bootdelay)
#endif
#ifdef CONFIG_ARCH_ROCKCHIP
if (!IS_ENABLED(CONFIG_CONSOLE_DISABLE_CLI) && ctrlc()) { /* we press ctrl+c ? */
if ((!IS_ENABLED(CONFIG_CONSOLE_DISABLE_CLI) && ctrlc()) || env_get("cli")) { /* we press ctrl+c ? */
#else
/*
* Check if key already pressed

13
sysdrv/source/uboot/u-boot/common/image-fit.c
View File

@@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#define FDT_DEFAULT_LOAD_ADDR 0x00c00000
#define __round_mask(x, y) ((__typeof__(x))((y)-1))
#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
@@ -2140,7 +2141,13 @@ int fit_image_load_index(bootm_headers_t *images, ulong addr,
ret = fit_image_select(fit, noffset, images->verify);
if (ret) {
bootstage_error(bootstage_id + BOOTSTAGE_SUB_HASH);
return ret;
/* Use the memory fdt directly */
printf(" Use the memory fdt directly\n");
*datap = FDT_DEFAULT_LOAD_ADDR;
fit_image_get_data_size(fit, noffset, (int *)&size);
*lenp = (ulong)size;
return noffset;
//return ret;
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
@@ -2260,8 +2267,10 @@ int fit_image_load_index(bootm_headers_t *images, ulong addr,
return -EXDEV;
}
//printf(" Loading %s from 0x%08lx to 0x%08lx\n",
// prop_name, data, load);
printf(" Loading %s from 0x%08lx to 0x%08lx\n",
prop_name, data, load);
prop_name, image_start, load);
dst = map_sysmem(load, len);
memmove(dst, buf, len);

151
sysdrv/source/uboot/u-boot/configs/luckfox_rv1106_uboot_defconfig Normal file
View File

@@ -0,0 +1,151 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
CONFIG_ROCKCHIP_RV1106=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_TARGET_EVB_RV1106=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="rv1106-evb"
CONFIG_DEBUG_UART=y
# CONFIG_DISTRO_DEFAULTS is not set
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
#CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_FIT_HW_CRYPTO=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
CONFIG_SPL_FIT_IMAGE_KB=256
CONFIG_SPL_FIT_IMAGE_MULTIPLE=1
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
# CONFIG_SKIP_RELOCATE_UBOOT is not set
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_MMC_WRITE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OPTEE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_RANDOM_UUID=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_BOOT_ANDROID=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_SCRIPT_UPDATE=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_U_BOOT_REMOVE_PROPS="interrupt-parent"
CONFIG_ENVF=y
CONFIG_ENVF_LIST="blkdevparts mtdparts sys_bootargs app reserved ipaddr serverip netmask gatewayip ethaddr"
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_SARADC_ROCKCHIP is not set
CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_CRYPTO=y
CONFIG_SPL_DM_CRYPTO=y
CONFIG_ROCKCHIP_CRYPTO_V2=y
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_ROCKCHIP_GPIO=y
# CONFIG_DM_I2C is not set
CONFIG_DM_KEY=y
CONFIG_ADC_KEY=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
# CONFIG_SUPPORT_EMMC_RPMB is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_MTD_BLK=y
CONFIG_MTD_DEVICE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0x3
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_RK630=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
# CONFIG_DWC_ETH_QOS_FULL is not set
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_DM_REGULATOR is not set
# CONFIG_DM_PWM is not set
CONFIG_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0xff4c0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
# CONFIG_SYSRESET_SYSCON_REBOOT is not set
# CONFIG_FAT_WRITE is not set
CONFIG_USE_TINY_PRINTF=y
# CONFIG_REGEX is not set
CONFIG_SPL_TINY_MEMSET=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_N_SIZE=0x200
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_SPL_LZMA=y
CONFIG_SPL_GZIP=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

1
sysdrv/source/uboot/u-boot/include/boot_rkimg.h
View File

@@ -19,6 +19,7 @@ enum _boot_mode {
BOOT_MODE_PANIC,
BOOT_MODE_WATCHDOG,
BOOT_MODE_DFU,
BOOT_MODE_UBOOT_TERMINAL,
BOOT_MODE_UNDEFINE,
};