mirror of
https://github.com/LuckfoxTECH/luckfox-pico.git
synced 2026-01-19 17:59:18 +01:00
project:build.sh: Added fastboot support; custom modifications to U-Boot and kernel implemented using patches.
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
This commit is contained in:
luckfox-eng29
13
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/SConscript
Normal file
13
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/SConscript
Normal file
@@ -0,0 +1,13 @@
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if rtconfig.PLATFORM == 'gcc':
|
||||
src += Glob('*_gcc.S')
|
||||
|
||||
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
227
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/context_gcc.S
Normal file
227
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/context_gcc.S
Normal file
@@ -0,0 +1,227 @@
|
||||
;/*
|
||||
; * File : context_gcc.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2018, RT-Thread Development Team
|
||||
; *
|
||||
; * This program is free software; you can redistribute it and/or modify
|
||||
; * it under the terms of the GNU General Public License as published by
|
||||
; * the Free Software Foundation; either version 2 of the License, or
|
||||
; * (at your option) any later version.
|
||||
; *
|
||||
; * This program is distributed in the hope that it will be useful,
|
||||
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; * GNU General Public License for more details.
|
||||
; *
|
||||
; * You should have received a copy of the GNU General Public License along
|
||||
; * with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2017-07-16 zhangjun for hifive1
|
||||
; * 2018-05-29 tanek optimize rt_hw_interrupt_*
|
||||
; * 2018-05-29 tanek add mie register to context
|
||||
; */
|
||||
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable(void);
|
||||
*/
|
||||
.globl rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
csrrci a0, mstatus, 8
|
||||
ret
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t level);
|
||||
*/
|
||||
.globl rt_hw_interrupt_enable
|
||||
rt_hw_interrupt_enable:
|
||||
csrw mstatus, a0
|
||||
ret
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||
* a0 --> from
|
||||
* a1 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
|
||||
/* saved from thread context
|
||||
* x1/ra -> sp(0)
|
||||
* x1/ra -> sp(1)
|
||||
* mstatus.mie -> sp(2)
|
||||
* x(i) -> sp(i-4)
|
||||
*/
|
||||
addi sp, sp, -32 * 4
|
||||
sw sp, (a0)
|
||||
|
||||
sw x1, 0 * 4(sp)
|
||||
sw x1, 1 * 4(sp)
|
||||
|
||||
csrr a0, mstatus
|
||||
andi a0, a0, 8
|
||||
beqz a0, save_mpie
|
||||
li a0, 0x80
|
||||
save_mpie:
|
||||
sw a0, 2 * 4(sp)
|
||||
|
||||
sw x4, 4 * 4(sp)
|
||||
sw x5, 5 * 4(sp)
|
||||
sw x6, 6 * 4(sp)
|
||||
sw x7, 7 * 4(sp)
|
||||
sw x8, 8 * 4(sp)
|
||||
sw x9, 9 * 4(sp)
|
||||
sw x10, 10 * 4(sp)
|
||||
sw x11, 11 * 4(sp)
|
||||
sw x12, 12 * 4(sp)
|
||||
sw x13, 13 * 4(sp)
|
||||
sw x14, 14 * 4(sp)
|
||||
sw x15, 15 * 4(sp)
|
||||
sw x16, 16 * 4(sp)
|
||||
sw x17, 17 * 4(sp)
|
||||
sw x18, 18 * 4(sp)
|
||||
sw x19, 19 * 4(sp)
|
||||
sw x20, 20 * 4(sp)
|
||||
sw x21, 21 * 4(sp)
|
||||
sw x22, 22 * 4(sp)
|
||||
sw x23, 23 * 4(sp)
|
||||
sw x24, 24 * 4(sp)
|
||||
sw x25, 25 * 4(sp)
|
||||
sw x26, 26 * 4(sp)
|
||||
sw x27, 27 * 4(sp)
|
||||
sw x28, 28 * 4(sp)
|
||||
sw x29, 29 * 4(sp)
|
||||
sw x30, 30 * 4(sp)
|
||||
sw x31, 31 * 4(sp)
|
||||
|
||||
/* restore to thread context
|
||||
* sp(0) -> epc;
|
||||
* sp(1) -> ra;
|
||||
* sp(i) -> x(i+2)
|
||||
*/
|
||||
lw sp, (a1)
|
||||
|
||||
/* resw ra to mepc */
|
||||
lw a1, 0 * 4(sp)
|
||||
csrw mepc, a1
|
||||
lw x1, 1 * 4(sp)
|
||||
|
||||
/* force to machin mode(MPP=11) */
|
||||
li a1, 0x00001800;
|
||||
csrs mstatus, a1
|
||||
lw a1, 2 * 4(sp)
|
||||
csrs mstatus, a1
|
||||
|
||||
lw x4, 4 * 4(sp)
|
||||
lw x5, 5 * 4(sp)
|
||||
lw x6, 6 * 4(sp)
|
||||
lw x7, 7 * 4(sp)
|
||||
lw x8, 8 * 4(sp)
|
||||
lw x9, 9 * 4(sp)
|
||||
lw x10, 10 * 4(sp)
|
||||
lw x11, 11 * 4(sp)
|
||||
lw x12, 12 * 4(sp)
|
||||
lw x13, 13 * 4(sp)
|
||||
lw x14, 14 * 4(sp)
|
||||
lw x15, 15 * 4(sp)
|
||||
lw x16, 16 * 4(sp)
|
||||
lw x17, 17 * 4(sp)
|
||||
lw x18, 18 * 4(sp)
|
||||
lw x19, 19 * 4(sp)
|
||||
lw x20, 20 * 4(sp)
|
||||
lw x21, 21 * 4(sp)
|
||||
lw x22, 22 * 4(sp)
|
||||
lw x23, 23 * 4(sp)
|
||||
lw x24, 24 * 4(sp)
|
||||
lw x25, 25 * 4(sp)
|
||||
lw x26, 26 * 4(sp)
|
||||
lw x27, 27 * 4(sp)
|
||||
lw x28, 28 * 4(sp)
|
||||
lw x29, 29 * 4(sp)
|
||||
lw x30, 30 * 4(sp)
|
||||
lw x31, 31 * 4(sp)
|
||||
|
||||
addi sp, sp, 32 * 4
|
||||
mret
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to);
|
||||
* a0 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
lw sp, (a0)
|
||||
|
||||
/* load epc from stack */
|
||||
lw a0, 0 * 4(sp)
|
||||
csrw mepc, a0
|
||||
lw x1, 1 * 4(sp)
|
||||
/* load mstatus from stack */
|
||||
lw a0, 2 * 4(sp)
|
||||
csrw mstatus, a0
|
||||
lw x4, 4 * 4(sp)
|
||||
lw x5, 5 * 4(sp)
|
||||
lw x6, 6 * 4(sp)
|
||||
lw x7, 7 * 4(sp)
|
||||
lw x8, 8 * 4(sp)
|
||||
lw x9, 9 * 4(sp)
|
||||
lw x10, 10 * 4(sp)
|
||||
lw x11, 11 * 4(sp)
|
||||
lw x12, 12 * 4(sp)
|
||||
lw x13, 13 * 4(sp)
|
||||
lw x14, 14 * 4(sp)
|
||||
lw x15, 15 * 4(sp)
|
||||
lw x16, 16 * 4(sp)
|
||||
lw x17, 17 * 4(sp)
|
||||
lw x18, 18 * 4(sp)
|
||||
lw x19, 19 * 4(sp)
|
||||
lw x20, 20 * 4(sp)
|
||||
lw x21, 21 * 4(sp)
|
||||
lw x22, 22 * 4(sp)
|
||||
lw x23, 23 * 4(sp)
|
||||
lw x24, 24 * 4(sp)
|
||||
lw x25, 25 * 4(sp)
|
||||
lw x26, 26 * 4(sp)
|
||||
lw x27, 27 * 4(sp)
|
||||
lw x28, 28 * 4(sp)
|
||||
lw x29, 29 * 4(sp)
|
||||
lw x30, 30 * 4(sp)
|
||||
lw x31, 31 * 4(sp)
|
||||
|
||||
addi sp, sp, 32 * 4
|
||||
mret
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
|
||||
*/
|
||||
.globl rt_thread_switch_interrupt_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
addi sp, sp, -16
|
||||
sw s0, 12(sp)
|
||||
sw a0, 8(sp)
|
||||
sw a5, 4(sp)
|
||||
|
||||
la a0, rt_thread_switch_interrupt_flag
|
||||
lw a5, (a0)
|
||||
bnez a5, _reswitch
|
||||
li a5, 1
|
||||
sw a5, (a0)
|
||||
|
||||
la a5, rt_interrupt_from_thread
|
||||
lw a0, 8(sp)
|
||||
sw a0, (a5)
|
||||
|
||||
_reswitch:
|
||||
la a5, rt_interrupt_to_thread
|
||||
sw a1, (a5)
|
||||
|
||||
lw a5, 4(sp)
|
||||
lw a0, 8(sp)
|
||||
lw s0, 12(sp)
|
||||
addi sp, sp, 16
|
||||
ret
|
||||
145
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/entry_gcc.S
Normal file
145
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/entry_gcc.S
Normal file
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* File : context_gcc.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2018, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-05-29 tanek first implementation
|
||||
*/
|
||||
|
||||
.section .text.entry
|
||||
.align 2
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
|
||||
// save all from thread context
|
||||
addi sp, sp, -32 * 4
|
||||
|
||||
sw x1, 1 * 4(sp)
|
||||
li t0, 0x80
|
||||
sw t0, 2 * 4(sp)
|
||||
|
||||
sw x4, 4 * 4(sp)
|
||||
sw x5, 5 * 4(sp)
|
||||
sw x6, 6 * 4(sp)
|
||||
sw x7, 7 * 4(sp)
|
||||
sw x8, 8 * 4(sp)
|
||||
sw x9, 9 * 4(sp)
|
||||
sw x10, 10 * 4(sp)
|
||||
sw x11, 11 * 4(sp)
|
||||
sw x12, 12 * 4(sp)
|
||||
sw x13, 13 * 4(sp)
|
||||
sw x14, 14 * 4(sp)
|
||||
sw x15, 15 * 4(sp)
|
||||
sw x16, 16 * 4(sp)
|
||||
sw x17, 17 * 4(sp)
|
||||
sw x18, 18 * 4(sp)
|
||||
sw x19, 19 * 4(sp)
|
||||
sw x20, 20 * 4(sp)
|
||||
sw x21, 21 * 4(sp)
|
||||
sw x22, 22 * 4(sp)
|
||||
sw x23, 23 * 4(sp)
|
||||
sw x24, 24 * 4(sp)
|
||||
sw x25, 25 * 4(sp)
|
||||
sw x26, 26 * 4(sp)
|
||||
sw x27, 27 * 4(sp)
|
||||
sw x28, 28 * 4(sp)
|
||||
sw x29, 29 * 4(sp)
|
||||
sw x30, 30 * 4(sp)
|
||||
sw x31, 31 * 4(sp)
|
||||
|
||||
// switch to interrupt stack
|
||||
move s0, sp
|
||||
la sp, _sp
|
||||
|
||||
// interrupt handle
|
||||
call rt_interrupt_enter
|
||||
csrr a0, mcause
|
||||
csrr a1, mepc
|
||||
mv a2, sp
|
||||
call handle_trap
|
||||
call rt_interrupt_leave
|
||||
|
||||
// switch to from thread stack
|
||||
move sp, s0
|
||||
|
||||
// need to switch new thread
|
||||
la s0, rt_thread_switch_interrupt_flag
|
||||
lw s2, 0(s0)
|
||||
beqz s2, spurious_interrupt
|
||||
sw zero, 0(s0)
|
||||
|
||||
csrr a0, mepc
|
||||
sw a0, 0 * 4(sp)
|
||||
|
||||
la s0, rt_interrupt_from_thread
|
||||
lw s1, 0(s0)
|
||||
sw sp, 0(s1)
|
||||
|
||||
la s0, rt_interrupt_to_thread
|
||||
lw s1, 0(s0)
|
||||
lw sp, 0(s1)
|
||||
|
||||
lw a0, 0 * 4(sp)
|
||||
csrw mepc, a0
|
||||
|
||||
spurious_interrupt:
|
||||
lw x1, 1 * 4(sp)
|
||||
|
||||
// Remain in M-mode after mret
|
||||
li t0, 0x00001800
|
||||
csrs mstatus, t0
|
||||
lw t0, 2 * 4(sp)
|
||||
csrs mstatus, t0
|
||||
|
||||
lw x4, 4 * 4(sp)
|
||||
lw x5, 5 * 4(sp)
|
||||
lw x6, 6 * 4(sp)
|
||||
lw x7, 7 * 4(sp)
|
||||
lw x8, 8 * 4(sp)
|
||||
lw x9, 9 * 4(sp)
|
||||
lw x10, 10 * 4(sp)
|
||||
lw x11, 11 * 4(sp)
|
||||
lw x12, 12 * 4(sp)
|
||||
lw x13, 13 * 4(sp)
|
||||
lw x14, 14 * 4(sp)
|
||||
lw x15, 15 * 4(sp)
|
||||
lw x16, 16 * 4(sp)
|
||||
lw x17, 17 * 4(sp)
|
||||
lw x18, 18 * 4(sp)
|
||||
lw x19, 19 * 4(sp)
|
||||
lw x20, 20 * 4(sp)
|
||||
lw x21, 21 * 4(sp)
|
||||
lw x22, 22 * 4(sp)
|
||||
lw x23, 23 * 4(sp)
|
||||
lw x24, 24 * 4(sp)
|
||||
lw x25, 25 * 4(sp)
|
||||
lw x26, 26 * 4(sp)
|
||||
lw x27, 27 * 4(sp)
|
||||
lw x28, 28 * 4(sp)
|
||||
lw x29, 29 * 4(sp)
|
||||
lw x30, 30 * 4(sp)
|
||||
lw x31, 31 * 4(sp)
|
||||
|
||||
addi sp, sp, 32 * 4
|
||||
mret
|
||||
|
||||
.weak handle_trap
|
||||
handle_trap:
|
||||
1:
|
||||
j 1b
|
||||
104
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/stack.c
Normal file
104
sysdrv/source/mcu/rt-thread/libcpu/risc-v/e310/stack.c
Normal file
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-07-31 tanek first implementation
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/* flag in interrupt handling */
|
||||
rt_uint32_t rt_interrupt_from_thread;
|
||||
rt_uint32_t rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
struct stack_frame
|
||||
{
|
||||
rt_ubase_t epc; /* epc - epc - program counter */
|
||||
rt_ubase_t ra; /* x1 - ra - return address for jumps */
|
||||
rt_ubase_t mstatus; /* - machine status register */
|
||||
rt_ubase_t gp; /* x3 - gp - global pointer */
|
||||
rt_ubase_t tp; /* x4 - tp - thread pointer */
|
||||
rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
|
||||
rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
|
||||
rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
|
||||
rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
|
||||
rt_ubase_t s1; /* x9 - s1 - saved register 1 */
|
||||
rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
|
||||
rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
|
||||
rt_ubase_t a2; /* x12 - a2 - function argument 2 */
|
||||
rt_ubase_t a3; /* x13 - a3 - function argument 3 */
|
||||
rt_ubase_t a4; /* x14 - a4 - function argument 4 */
|
||||
rt_ubase_t a5; /* x15 - a5 - function argument 5 */
|
||||
rt_ubase_t a6; /* x16 - a6 - function argument 6 */
|
||||
rt_ubase_t a7; /* x17 - s7 - function argument 7 */
|
||||
rt_ubase_t s2; /* x18 - s2 - saved register 2 */
|
||||
rt_ubase_t s3; /* x19 - s3 - saved register 3 */
|
||||
rt_ubase_t s4; /* x20 - s4 - saved register 4 */
|
||||
rt_ubase_t s5; /* x21 - s5 - saved register 5 */
|
||||
rt_ubase_t s6; /* x22 - s6 - saved register 6 */
|
||||
rt_ubase_t s7; /* x23 - s7 - saved register 7 */
|
||||
rt_ubase_t s8; /* x24 - s8 - saved register 8 */
|
||||
rt_ubase_t s9; /* x25 - s9 - saved register 9 */
|
||||
rt_ubase_t s10; /* x26 - s10 - saved register 10 */
|
||||
rt_ubase_t s11; /* x27 - s11 - saved register 11 */
|
||||
rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
|
||||
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
|
||||
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
|
||||
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
|
||||
};
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
struct stack_frame *stack_frame;
|
||||
rt_uint8_t *stk;
|
||||
int i;
|
||||
|
||||
stk = stack_addr + sizeof(rt_uint32_t);
|
||||
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
|
||||
stk -= sizeof(struct stack_frame);
|
||||
|
||||
stack_frame = (struct stack_frame *)stk;
|
||||
|
||||
for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_ubase_t); i++)
|
||||
{
|
||||
((rt_ubase_t *)stack_frame)[i] = 0xdeadbeef;
|
||||
}
|
||||
|
||||
stack_frame->ra = (rt_ubase_t)texit;
|
||||
stack_frame->a0 = (rt_ubase_t)parameter;
|
||||
stack_frame->epc = (rt_ubase_t)tentry;
|
||||
|
||||
// force to machine mode(MPP=11) and set MPIE to 1
|
||||
stack_frame->mstatus = 0x00001880;
|
||||
|
||||
return stk;
|
||||
}
|
||||
13
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/SConscript
Normal file
13
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/SConscript
Normal file
@@ -0,0 +1,13 @@
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if rtconfig.PLATFORM == 'gcc':
|
||||
src += Glob('*_gcc.S')
|
||||
|
||||
group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
227
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/context_gcc.S
Normal file
227
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/context_gcc.S
Normal file
@@ -0,0 +1,227 @@
|
||||
;/*
|
||||
; * File : context_gcc.S
|
||||
; * This file is part of RT-Thread RTOS
|
||||
; * COPYRIGHT (C) 2018, RT-Thread Development Team
|
||||
; *
|
||||
; * This program is free software; you can redistribute it and/or modify
|
||||
; * it under the terms of the GNU General Public License as published by
|
||||
; * the Free Software Foundation; either version 2 of the License, or
|
||||
; * (at your option) any later version.
|
||||
; *
|
||||
; * This program is distributed in the hope that it will be useful,
|
||||
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; * GNU General Public License for more details.
|
||||
; *
|
||||
; * You should have received a copy of the GNU General Public License along
|
||||
; * with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
; *
|
||||
; * Change Logs:
|
||||
; * Date Author Notes
|
||||
; * 2017-07-16 zhangjun for hifive1
|
||||
; * 2018-05-29 tanek optimize rt_hw_interrupt_*
|
||||
; * 2018-05-29 tanek add mie register to context
|
||||
; */
|
||||
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable(void);
|
||||
*/
|
||||
.globl rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
csrrci a0, mstatus, 8
|
||||
ret
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t level);
|
||||
*/
|
||||
.globl rt_hw_interrupt_enable
|
||||
rt_hw_interrupt_enable:
|
||||
csrw mstatus, a0
|
||||
ret
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||
* a0 --> from
|
||||
* a1 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
|
||||
/* saved from thread context
|
||||
* x1/ra -> sp(0)
|
||||
* x1/ra -> sp(1)
|
||||
* mstatus.mie -> sp(2)
|
||||
* x(i) -> sp(i-4)
|
||||
*/
|
||||
addi sp, sp, -32 * 4
|
||||
sw sp, (a0)
|
||||
|
||||
sw x1, 0 * 4(sp)
|
||||
sw x1, 1 * 4(sp)
|
||||
|
||||
csrr a0, mstatus
|
||||
andi a0, a0, 8
|
||||
beqz a0, save_mpie
|
||||
li a0, 0x80
|
||||
save_mpie:
|
||||
sw a0, 2 * 4(sp)
|
||||
|
||||
sw x4, 4 * 4(sp)
|
||||
sw x5, 5 * 4(sp)
|
||||
sw x6, 6 * 4(sp)
|
||||
sw x7, 7 * 4(sp)
|
||||
sw x8, 8 * 4(sp)
|
||||
sw x9, 9 * 4(sp)
|
||||
sw x10, 10 * 4(sp)
|
||||
sw x11, 11 * 4(sp)
|
||||
sw x12, 12 * 4(sp)
|
||||
sw x13, 13 * 4(sp)
|
||||
sw x14, 14 * 4(sp)
|
||||
sw x15, 15 * 4(sp)
|
||||
sw x16, 16 * 4(sp)
|
||||
sw x17, 17 * 4(sp)
|
||||
sw x18, 18 * 4(sp)
|
||||
sw x19, 19 * 4(sp)
|
||||
sw x20, 20 * 4(sp)
|
||||
sw x21, 21 * 4(sp)
|
||||
sw x22, 22 * 4(sp)
|
||||
sw x23, 23 * 4(sp)
|
||||
sw x24, 24 * 4(sp)
|
||||
sw x25, 25 * 4(sp)
|
||||
sw x26, 26 * 4(sp)
|
||||
sw x27, 27 * 4(sp)
|
||||
sw x28, 28 * 4(sp)
|
||||
sw x29, 29 * 4(sp)
|
||||
sw x30, 30 * 4(sp)
|
||||
sw x31, 31 * 4(sp)
|
||||
|
||||
/* restore to thread context
|
||||
* sp(0) -> epc;
|
||||
* sp(1) -> ra;
|
||||
* sp(i) -> x(i+2)
|
||||
*/
|
||||
lw sp, (a1)
|
||||
|
||||
/* resw ra to mepc */
|
||||
lw a1, 0 * 4(sp)
|
||||
csrw mepc, a1
|
||||
lw x1, 1 * 4(sp)
|
||||
|
||||
/* force to machin mode(MPP=11) */
|
||||
li a1, 0x00001800;
|
||||
csrs mstatus, a1
|
||||
lw a1, 2 * 4(sp)
|
||||
csrs mstatus, a1
|
||||
|
||||
lw x4, 4 * 4(sp)
|
||||
lw x5, 5 * 4(sp)
|
||||
lw x6, 6 * 4(sp)
|
||||
lw x7, 7 * 4(sp)
|
||||
lw x8, 8 * 4(sp)
|
||||
lw x9, 9 * 4(sp)
|
||||
lw x10, 10 * 4(sp)
|
||||
lw x11, 11 * 4(sp)
|
||||
lw x12, 12 * 4(sp)
|
||||
lw x13, 13 * 4(sp)
|
||||
lw x14, 14 * 4(sp)
|
||||
lw x15, 15 * 4(sp)
|
||||
lw x16, 16 * 4(sp)
|
||||
lw x17, 17 * 4(sp)
|
||||
lw x18, 18 * 4(sp)
|
||||
lw x19, 19 * 4(sp)
|
||||
lw x20, 20 * 4(sp)
|
||||
lw x21, 21 * 4(sp)
|
||||
lw x22, 22 * 4(sp)
|
||||
lw x23, 23 * 4(sp)
|
||||
lw x24, 24 * 4(sp)
|
||||
lw x25, 25 * 4(sp)
|
||||
lw x26, 26 * 4(sp)
|
||||
lw x27, 27 * 4(sp)
|
||||
lw x28, 28 * 4(sp)
|
||||
lw x29, 29 * 4(sp)
|
||||
lw x30, 30 * 4(sp)
|
||||
lw x31, 31 * 4(sp)
|
||||
|
||||
addi sp, sp, 32 * 4
|
||||
mret
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to);
|
||||
* a0 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
lw sp, (a0)
|
||||
|
||||
/* load epc from stack */
|
||||
lw a0, 0 * 4(sp)
|
||||
csrw mepc, a0
|
||||
lw x1, 1 * 4(sp)
|
||||
/* load mstatus from stack */
|
||||
lw a0, 2 * 4(sp)
|
||||
csrw mstatus, a0
|
||||
lw x4, 4 * 4(sp)
|
||||
lw x5, 5 * 4(sp)
|
||||
lw x6, 6 * 4(sp)
|
||||
lw x7, 7 * 4(sp)
|
||||
lw x8, 8 * 4(sp)
|
||||
lw x9, 9 * 4(sp)
|
||||
lw x10, 10 * 4(sp)
|
||||
lw x11, 11 * 4(sp)
|
||||
lw x12, 12 * 4(sp)
|
||||
lw x13, 13 * 4(sp)
|
||||
lw x14, 14 * 4(sp)
|
||||
lw x15, 15 * 4(sp)
|
||||
lw x16, 16 * 4(sp)
|
||||
lw x17, 17 * 4(sp)
|
||||
lw x18, 18 * 4(sp)
|
||||
lw x19, 19 * 4(sp)
|
||||
lw x20, 20 * 4(sp)
|
||||
lw x21, 21 * 4(sp)
|
||||
lw x22, 22 * 4(sp)
|
||||
lw x23, 23 * 4(sp)
|
||||
lw x24, 24 * 4(sp)
|
||||
lw x25, 25 * 4(sp)
|
||||
lw x26, 26 * 4(sp)
|
||||
lw x27, 27 * 4(sp)
|
||||
lw x28, 28 * 4(sp)
|
||||
lw x29, 29 * 4(sp)
|
||||
lw x30, 30 * 4(sp)
|
||||
lw x31, 31 * 4(sp)
|
||||
|
||||
addi sp, sp, 32 * 4
|
||||
mret
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
|
||||
*/
|
||||
.globl rt_thread_switch_interrupt_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
addi sp, sp, -16
|
||||
sw s0, 12(sp)
|
||||
sw a0, 8(sp)
|
||||
sw a5, 4(sp)
|
||||
|
||||
la a0, rt_thread_switch_interrupt_flag
|
||||
lw a5, (a0)
|
||||
bnez a5, _reswitch
|
||||
li a5, 1
|
||||
sw a5, (a0)
|
||||
|
||||
la a5, rt_interrupt_from_thread
|
||||
lw a0, 8(sp)
|
||||
sw a0, (a5)
|
||||
|
||||
_reswitch:
|
||||
la a5, rt_interrupt_to_thread
|
||||
sw a1, (a5)
|
||||
|
||||
lw a5, 4(sp)
|
||||
lw a0, 8(sp)
|
||||
lw s0, 12(sp)
|
||||
addi sp, sp, 16
|
||||
ret
|
||||
146
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/entry_gcc.S
Normal file
146
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/entry_gcc.S
Normal file
@@ -0,0 +1,146 @@
|
||||
/*
|
||||
* File : context_gcc.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2018, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-05-29 tanek first implementation
|
||||
*/
|
||||
|
||||
.section .text.entry
|
||||
.align 6
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
|
||||
// save all from thread context
|
||||
addi sp, sp, -32 * 4
|
||||
|
||||
sw x1, 1 * 4(sp)
|
||||
|
||||
sw x4, 4 * 4(sp)
|
||||
sw x5, 5 * 4(sp)
|
||||
sw x6, 6 * 4(sp)
|
||||
sw x7, 7 * 4(sp)
|
||||
sw x8, 8 * 4(sp)
|
||||
sw x9, 9 * 4(sp)
|
||||
sw x10, 10 * 4(sp)
|
||||
sw x11, 11 * 4(sp)
|
||||
sw x12, 12 * 4(sp)
|
||||
sw x13, 13 * 4(sp)
|
||||
sw x14, 14 * 4(sp)
|
||||
sw x15, 15 * 4(sp)
|
||||
sw x16, 16 * 4(sp)
|
||||
sw x17, 17 * 4(sp)
|
||||
sw x18, 18 * 4(sp)
|
||||
sw x19, 19 * 4(sp)
|
||||
sw x20, 20 * 4(sp)
|
||||
sw x21, 21 * 4(sp)
|
||||
sw x22, 22 * 4(sp)
|
||||
sw x23, 23 * 4(sp)
|
||||
sw x24, 24 * 4(sp)
|
||||
sw x25, 25 * 4(sp)
|
||||
sw x26, 26 * 4(sp)
|
||||
sw x27, 27 * 4(sp)
|
||||
sw x28, 28 * 4(sp)
|
||||
sw x29, 29 * 4(sp)
|
||||
sw x30, 30 * 4(sp)
|
||||
sw x31, 31 * 4(sp)
|
||||
|
||||
li t0, 0x80
|
||||
sw t0, 2 * 4(sp)
|
||||
|
||||
// switch to interrupt stack
|
||||
move s0, sp
|
||||
la sp, _sp
|
||||
|
||||
// interrupt handle
|
||||
call rt_interrupt_enter
|
||||
csrr a0, mcause
|
||||
csrr a1, mepc
|
||||
mv a2, s0
|
||||
call handle_trap
|
||||
call rt_interrupt_leave
|
||||
|
||||
// switch to from thread stack
|
||||
move sp, s0
|
||||
|
||||
// need to switch new thread
|
||||
la s0, rt_thread_switch_interrupt_flag
|
||||
lw s2, 0(s0)
|
||||
beqz s2, spurious_interrupt
|
||||
sw zero, 0(s0)
|
||||
|
||||
csrr a0, mepc
|
||||
sw a0, 0 * 4(sp)
|
||||
|
||||
la s0, rt_interrupt_from_thread
|
||||
lw s1, 0(s0)
|
||||
sw sp, 0(s1)
|
||||
|
||||
la s0, rt_interrupt_to_thread
|
||||
lw s1, 0(s0)
|
||||
lw sp, 0(s1)
|
||||
|
||||
lw a0, 0 * 4(sp)
|
||||
csrw mepc, a0
|
||||
|
||||
spurious_interrupt:
|
||||
lw x1, 1 * 4(sp)
|
||||
|
||||
// Remain in M-mode after mret
|
||||
li t0, 0x00001800
|
||||
csrs mstatus, t0
|
||||
lw t0, 2 * 4(sp)
|
||||
csrs mstatus, t0
|
||||
|
||||
lw x4, 4 * 4(sp)
|
||||
lw x5, 5 * 4(sp)
|
||||
lw x6, 6 * 4(sp)
|
||||
lw x7, 7 * 4(sp)
|
||||
lw x8, 8 * 4(sp)
|
||||
lw x9, 9 * 4(sp)
|
||||
lw x10, 10 * 4(sp)
|
||||
lw x11, 11 * 4(sp)
|
||||
lw x12, 12 * 4(sp)
|
||||
lw x13, 13 * 4(sp)
|
||||
lw x14, 14 * 4(sp)
|
||||
lw x15, 15 * 4(sp)
|
||||
lw x16, 16 * 4(sp)
|
||||
lw x17, 17 * 4(sp)
|
||||
lw x18, 18 * 4(sp)
|
||||
lw x19, 19 * 4(sp)
|
||||
lw x20, 20 * 4(sp)
|
||||
lw x21, 21 * 4(sp)
|
||||
lw x22, 22 * 4(sp)
|
||||
lw x23, 23 * 4(sp)
|
||||
lw x24, 24 * 4(sp)
|
||||
lw x25, 25 * 4(sp)
|
||||
lw x26, 26 * 4(sp)
|
||||
lw x27, 27 * 4(sp)
|
||||
lw x28, 28 * 4(sp)
|
||||
lw x29, 29 * 4(sp)
|
||||
lw x30, 30 * 4(sp)
|
||||
lw x31, 31 * 4(sp)
|
||||
|
||||
addi sp, sp, 32 * 4
|
||||
mret
|
||||
|
||||
.weak handle_trap
|
||||
handle_trap:
|
||||
1:
|
||||
j 1b
|
||||
409
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/interrupt.c
Normal file
409
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/interrupt.c
Normal file
@@ -0,0 +1,409 @@
|
||||
/**
|
||||
* Copyright (c) 2020 Rockchip Electronic Co.,Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
******************************************************************************
|
||||
* @file interrupt.c
|
||||
* @author Jason Zhu
|
||||
* @version V0.1
|
||||
* @date 23-Feb-2020
|
||||
* @brief
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include "board.h"
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
|
||||
#else
|
||||
#define DEBUG_PRINTF(...)
|
||||
#endif
|
||||
|
||||
static struct rt_irq_desc irq_desc[MAX_HANDLERS];
|
||||
static struct rt_irq_desc soft_irq_desc;
|
||||
|
||||
extern void trap_entry();
|
||||
|
||||
static void write_csr_ipic(unsigned int addr, unsigned int val)
|
||||
{
|
||||
switch (addr)
|
||||
{
|
||||
case IPIC_CISV :
|
||||
write_csr(0xbf0, val);
|
||||
break;
|
||||
case IPIC_CICSR :
|
||||
write_csr(0xbf1, val);
|
||||
break;
|
||||
case IPIC_IPR :
|
||||
write_csr(0xbf2, val);
|
||||
break;
|
||||
case IPIC_ISVR :
|
||||
write_csr(0xbf3, val);
|
||||
break;
|
||||
case IPIC_EOI :
|
||||
write_csr(0xbf4, val);
|
||||
break;
|
||||
case IPIC_SOI :
|
||||
write_csr(0xbf5, val);
|
||||
break;
|
||||
case IPIC_IDX :
|
||||
write_csr(0xbf6, val);
|
||||
break;
|
||||
case IPIC_ICSR :
|
||||
write_csr(0xbf7, val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
static unsigned int read_csr_ipic(unsigned int addr)
|
||||
{
|
||||
unsigned int res;
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
case IPIC_CISV :
|
||||
res = read_csr(0xbf0);
|
||||
break;
|
||||
case IPIC_CICSR :
|
||||
res = read_csr(0xbf1);
|
||||
break;
|
||||
case IPIC_IPR :
|
||||
res = read_csr(0xbf2);
|
||||
break;
|
||||
case IPIC_ISVR :
|
||||
res = read_csr(0xbf3);
|
||||
break;
|
||||
case IPIC_EOI :
|
||||
res = read_csr(0xbf4);
|
||||
break;
|
||||
case IPIC_SOI :
|
||||
res = read_csr(0xbf5);
|
||||
break;
|
||||
case IPIC_IDX :
|
||||
res = read_csr(0xbf6);
|
||||
break;
|
||||
case IPIC_ICSR :
|
||||
res = read_csr(0xbf7);
|
||||
break;
|
||||
default:
|
||||
res = 0;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static void m_ext_irq_init()
|
||||
{
|
||||
set_csr(mie, MIP_MEIP);
|
||||
}
|
||||
|
||||
static void m_soft_irq_init()
|
||||
{
|
||||
set_csr(mie, MIP_MSIP);
|
||||
}
|
||||
|
||||
static void m_ext_irq_handle(void)
|
||||
{
|
||||
rt_isr_handler_t isr_func;
|
||||
rt_uint32_t irq;
|
||||
void *param;
|
||||
|
||||
/* Any value can be written in IPIC_SOI to start process */
|
||||
write_csr_ipic(IPIC_SOI, 0x0);
|
||||
irq = rt_hw_interrupt_get_active();
|
||||
rt_hw_interrupt_mask(irq);
|
||||
/* get interrupt service routine */
|
||||
isr_func = irq_desc[irq].handler;
|
||||
param = irq_desc[irq].param;
|
||||
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(irq, param);
|
||||
/* Any value can be written in IPIC_EOI to end process */
|
||||
write_csr_ipic(IPIC_EOI, 0x0);
|
||||
rt_hw_interrupt_umask(irq);
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
irq_desc[irq].counter ++;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void m_soft_irq_handle(void)
|
||||
{
|
||||
rt_isr_handler_t isr_func;
|
||||
void *param;
|
||||
|
||||
clear_csr(mie, MIP_MSIP);
|
||||
/* get interrupt service routine */
|
||||
isr_func = soft_irq_desc.handler;
|
||||
param = soft_irq_desc.param;
|
||||
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(0, param);
|
||||
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
soft_irq_desc.counter ++;
|
||||
#endif
|
||||
set_csr(mie, MIP_MSIP);
|
||||
}
|
||||
|
||||
static void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
_update_timer();
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
struct exception_stack_frame
|
||||
{
|
||||
uint32_t x1;
|
||||
uint32_t x2;
|
||||
uint32_t x3;
|
||||
uint32_t x4;
|
||||
uint32_t x5;
|
||||
uint32_t x6;
|
||||
uint32_t x7;
|
||||
uint32_t x8;
|
||||
uint32_t x9;
|
||||
uint32_t x10;
|
||||
uint32_t x11;
|
||||
uint32_t x12;
|
||||
uint32_t x13;
|
||||
uint32_t x14;
|
||||
uint32_t x15;
|
||||
uint32_t x16;
|
||||
uint32_t x17;
|
||||
uint32_t x18;
|
||||
uint32_t x19;
|
||||
uint32_t x20;
|
||||
uint32_t x21;
|
||||
uint32_t x22;
|
||||
uint32_t x23;
|
||||
uint32_t x24;
|
||||
uint32_t x25;
|
||||
uint32_t x26;
|
||||
uint32_t x27;
|
||||
uint32_t x28;
|
||||
uint32_t x29;
|
||||
uint32_t x30;
|
||||
uint32_t x31;
|
||||
};
|
||||
|
||||
void print_stack_frame(unsigned int sp)
|
||||
{
|
||||
struct exception_stack_frame *esf = (struct exception_stack_frame *)(sp + 4);
|
||||
|
||||
rt_kprintf("\n=================================================================\n");
|
||||
rt_kprintf("x1 (ra : Return address ) ==> 0x%08x\n", esf->x1);
|
||||
rt_kprintf("x2 (sp : Stack pointer ) ==> 0x%08x\n", esf->x2);
|
||||
rt_kprintf("x3 (gp : Global pointer ) ==> 0x%08x\n", esf->x3);
|
||||
rt_kprintf("x4 (tp : Thread pointer ) ==> 0x%08x\n", esf->x4);
|
||||
rt_kprintf("x5 (t0 : Temporary ) ==> 0x%08x\n", esf->x5);
|
||||
rt_kprintf("x6 (t1 : Temporary ) ==> 0x%08x\n", esf->x6);
|
||||
rt_kprintf("x7 (t2 : Temporary ) ==> 0x%08x\n", esf->x7);
|
||||
rt_kprintf("x8 (s0/fp: Save register,frame pointer ) ==> 0x%08x\n", esf->x8);
|
||||
rt_kprintf("x9 (s1 : Save register ) ==> 0x%08x\n", esf->x9);
|
||||
rt_kprintf("x10(a0 : Function argument,return value) ==> 0x%08x\n", esf->x10);
|
||||
rt_kprintf("x11(a1 : Function argument,return value) ==> 0x%08x\n", esf->x11);
|
||||
rt_kprintf("x12(a2 : Function argument ) ==> 0x%08x\n", esf->x12);
|
||||
rt_kprintf("x13(a3 : Function argument ) ==> 0x%08x\n", esf->x13);
|
||||
rt_kprintf("x14(a4 : Function argument ) ==> 0x%08x\n", esf->x14);
|
||||
rt_kprintf("x15(a5 : Function argument ) ==> 0x%08x\n", esf->x15);
|
||||
rt_kprintf("x16(a6 : Function argument ) ==> 0x%08x\n", esf->x16);
|
||||
rt_kprintf("x17(a7 : Function argument ) ==> 0x%08x\n", esf->x17);
|
||||
rt_kprintf("x18(s2 : Save register ) ==> 0x%08x\n", esf->x18);
|
||||
rt_kprintf("x19(s3 : Save register ) ==> 0x%08x\n", esf->x19);
|
||||
rt_kprintf("x20(s4 : Save register ) ==> 0x%08x\n", esf->x20);
|
||||
rt_kprintf("x21(s5 : Save register ) ==> 0x%08x\n", esf->x21);
|
||||
rt_kprintf("x22(s6 : Save register ) ==> 0x%08x\n", esf->x22);
|
||||
rt_kprintf("x23(s7 : Save register ) ==> 0x%08x\n", esf->x23);
|
||||
rt_kprintf("x24(s8 : Save register ) ==> 0x%08x\n", esf->x24);
|
||||
rt_kprintf("x25(s9 : Save register ) ==> 0x%08x\n", esf->x25);
|
||||
rt_kprintf("x26(s10 : Save register ) ==> 0x%08x\n", esf->x26);
|
||||
rt_kprintf("x27(s11 : Save register ) ==> 0x%08x\n", esf->x27);
|
||||
rt_kprintf("x28(t3 : Temporary ) ==> 0x%08x\n", esf->x28);
|
||||
rt_kprintf("x29(t4 : Temporary ) ==> 0x%08x\n", esf->x29);
|
||||
rt_kprintf("x30(t5 : Temporary ) ==> 0x%08x\n", esf->x30);
|
||||
rt_kprintf("x31(t6 : Temporary ) ==> 0x%08x\n", esf->x31);
|
||||
rt_kprintf("=================================================================\n");
|
||||
}
|
||||
|
||||
void handle_trap(unsigned int i_mcause, unsigned int i_mepc, unsigned int i_sp)
|
||||
{
|
||||
DEBUG_PRINTF("mcasue 0x%x, i_mepc is 0x%x, i_sp is 0x%x\n", i_mcause, i_mepc, i_sp);
|
||||
unsigned int mcause = i_mcause & 0x7fffffff;
|
||||
|
||||
if ((i_mcause & 0x80000000) == 0x80000000)
|
||||
{
|
||||
/* environment interrupt */
|
||||
switch (mcause)
|
||||
{
|
||||
case IRQ_S_SOFT:
|
||||
rt_kprintf("s_soft irq enter\n");
|
||||
break;
|
||||
case IRQ_H_SOFT:
|
||||
rt_kprintf("h_soft irq enter\n");
|
||||
break;
|
||||
case IRQ_M_SOFT:
|
||||
m_soft_irq_handle();
|
||||
break;
|
||||
case IRQ_S_TIMER:
|
||||
rt_kprintf("s_timer irq enter\n");
|
||||
break;
|
||||
case IRQ_H_TIMER:
|
||||
rt_kprintf("h_timer irq enter\n");
|
||||
break;
|
||||
case IRQ_M_TIMER:
|
||||
SysTick_Handler();
|
||||
break;
|
||||
case IRQ_S_EXT:
|
||||
rt_kprintf("s_ext irq enter\n");
|
||||
break;
|
||||
case IRQ_H_EXT:
|
||||
rt_kprintf("h_ext irq enter\n");
|
||||
break;
|
||||
case IRQ_M_EXT:
|
||||
m_ext_irq_handle();
|
||||
break;
|
||||
case IRQ_COP:
|
||||
rt_kprintf("cop irq enter\n");
|
||||
break;
|
||||
case IRQ_HOST:
|
||||
rt_kprintf("host irq enter\n");
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("Environment interrupt not implecation, mcause is 0x%x\n", i_mcause);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* system interrupt */
|
||||
switch (mcause)
|
||||
{
|
||||
case EXC_IAM:
|
||||
rt_kprintf("Instruction address misaligned\n");
|
||||
break;
|
||||
case EXC_IAF:
|
||||
rt_kprintf("Instruction access fault\n");
|
||||
break;
|
||||
case EXC_II:
|
||||
rt_kprintf("Illegal instruction\n");
|
||||
break;
|
||||
case EXC_BP:
|
||||
write_csr(mepc, i_mepc + 4);
|
||||
rt_kprintf("Breakpoint\n");
|
||||
break;
|
||||
case EXC_LAM:
|
||||
rt_kprintf("Load address misaligned\n");
|
||||
break;
|
||||
case EXC_LAF:
|
||||
rt_kprintf("Load access fault\n");
|
||||
break;
|
||||
case EXC_SAM:
|
||||
rt_kprintf("Store/AMO address misaligned\n");
|
||||
break;
|
||||
case EXC_SAF:
|
||||
rt_kprintf("Store/AMO access fault\n");
|
||||
break;
|
||||
case EXC_ECFU:
|
||||
rt_kprintf("Environment call from U-mode\n");
|
||||
break;
|
||||
case EXC_ECFS:
|
||||
rt_kprintf("Environment call from S-mode\n");
|
||||
break;
|
||||
case EXC_ECFM:
|
||||
write_csr(mepc, i_mepc + 4);
|
||||
rt_kprintf("Environment call from M-mode\n");
|
||||
break;
|
||||
case EXC_IPF:
|
||||
rt_kprintf("Instruction page fault\n");
|
||||
break;
|
||||
case EXC_LPF:
|
||||
rt_kprintf("Load page fault\n");
|
||||
break;
|
||||
case EXC_SPF:
|
||||
rt_kprintf("Store/AMO page fault\n");
|
||||
break;
|
||||
default:
|
||||
rt_kprintf("System interrupt not implecation, mcause is 0x%x\n", i_mcause);
|
||||
}
|
||||
print_stack_frame(i_sp);
|
||||
rt_kprintf("exception pc => 0x%08x\n", i_mepc);
|
||||
rt_kprintf("stack pointer => 0x%08x\n", i_sp);
|
||||
while (1);
|
||||
}
|
||||
}
|
||||
|
||||
RT_WEAK void rt_hw_interrupt_active(int vector) {}
|
||||
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
write_csr(mtvec, &trap_entry);
|
||||
m_ext_irq_init();
|
||||
m_soft_irq_init();
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
/* only mask int_mux */
|
||||
rt_hw_interrupt_deactive(vector);
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
rt_hw_interrupt_active(vector);
|
||||
}
|
||||
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if (vector < MAX_HANDLERS)
|
||||
{
|
||||
old_handler = irq_desc[vector].handler;
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
irq_desc[vector].handler = (rt_isr_handler_t)handler;
|
||||
irq_desc[vector].param = param;
|
||||
/* enable interrupt vector as default */
|
||||
write_csr_ipic(IPIC_IDX, vector / INTERRUPT_SEPERATE);
|
||||
write_csr_ipic(IPIC_ICSR, IPIC_ICSR_IE);
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
|
||||
irq_desc[vector].counter = 0;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
rt_isr_handler_t rt_soft_interrupt_install(rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
old_handler = soft_irq_desc.handler;
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
soft_irq_desc.handler = (rt_isr_handler_t)handler;
|
||||
soft_irq_desc.param = param;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_snprintf(soft_irq_desc.name, RT_NAME_MAX - 1, "%s", name);
|
||||
soft_irq_desc.counter = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
104
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/stack.c
Normal file
104
sysdrv/source/mcu/rt-thread/libcpu/risc-v/scr1/stack.c
Normal file
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-07-31 tanek first implementation
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/* flag in interrupt handling */
|
||||
rt_uint32_t rt_interrupt_from_thread;
|
||||
rt_uint32_t rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
struct stack_frame
|
||||
{
|
||||
rt_ubase_t epc; /* epc - epc - program counter */
|
||||
rt_ubase_t ra; /* x1 - ra - return address for jumps */
|
||||
rt_ubase_t mstatus; /* - machine status register */
|
||||
rt_ubase_t gp; /* x3 - gp - global pointer */
|
||||
rt_ubase_t tp; /* x4 - tp - thread pointer */
|
||||
rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
|
||||
rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
|
||||
rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
|
||||
rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
|
||||
rt_ubase_t s1; /* x9 - s1 - saved register 1 */
|
||||
rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
|
||||
rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
|
||||
rt_ubase_t a2; /* x12 - a2 - function argument 2 */
|
||||
rt_ubase_t a3; /* x13 - a3 - function argument 3 */
|
||||
rt_ubase_t a4; /* x14 - a4 - function argument 4 */
|
||||
rt_ubase_t a5; /* x15 - a5 - function argument 5 */
|
||||
rt_ubase_t a6; /* x16 - a6 - function argument 6 */
|
||||
rt_ubase_t a7; /* x17 - s7 - function argument 7 */
|
||||
rt_ubase_t s2; /* x18 - s2 - saved register 2 */
|
||||
rt_ubase_t s3; /* x19 - s3 - saved register 3 */
|
||||
rt_ubase_t s4; /* x20 - s4 - saved register 4 */
|
||||
rt_ubase_t s5; /* x21 - s5 - saved register 5 */
|
||||
rt_ubase_t s6; /* x22 - s6 - saved register 6 */
|
||||
rt_ubase_t s7; /* x23 - s7 - saved register 7 */
|
||||
rt_ubase_t s8; /* x24 - s8 - saved register 8 */
|
||||
rt_ubase_t s9; /* x25 - s9 - saved register 9 */
|
||||
rt_ubase_t s10; /* x26 - s10 - saved register 10 */
|
||||
rt_ubase_t s11; /* x27 - s11 - saved register 11 */
|
||||
rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
|
||||
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
|
||||
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
|
||||
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
|
||||
};
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
struct stack_frame *stack_frame;
|
||||
rt_uint8_t *stk;
|
||||
int i;
|
||||
|
||||
stk = stack_addr + sizeof(rt_uint32_t);
|
||||
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
|
||||
stk -= sizeof(struct stack_frame);
|
||||
|
||||
stack_frame = (struct stack_frame *)stk;
|
||||
|
||||
for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_ubase_t); i++)
|
||||
{
|
||||
((rt_ubase_t *)stack_frame)[i] = 0xdeadbeef;
|
||||
}
|
||||
|
||||
stack_frame->ra = (rt_ubase_t)texit;
|
||||
stack_frame->a0 = (rt_ubase_t)parameter;
|
||||
stack_frame->epc = (rt_ubase_t)tentry;
|
||||
|
||||
// force to machine mode(MPP=11) and set MPIE to 1
|
||||
stack_frame->mstatus = 0x00001880;
|
||||
|
||||
return stk;
|
||||
}
|
||||
Reference in New Issue
Block a user