project:build.sh: Added fastboot support; custom modifications to U-Boot and kernel implemented using patches.

project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between
the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door
for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more
usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp:
Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for
compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem.
sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device
tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately.
sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick
boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades.
sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for
fastboot.

Signed-off-by: luckfox-eng29 <eng29@luckfox.com>

sysdrv/source/mcu/rt-thread/components/drivers/i2c/SConscript

@@ -0,0 +1,18 @@
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+src = Split("""
+i2c_core.c
+i2c_dev.c
+""")
+
+if GetDepend('RT_USING_I2C_BITOPS'):
+    src = src + ['i2c-bit-ops.c']
+
+# The set of source files associated with this SConscript file.
+path = [cwd + '/../include']
+
+group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_I2C'], CPPPATH = path)
+
+Return('group')

sysdrv/source/mcu/rt-thread/components/drivers/i2c/fm24clxx.c

@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-07-14     aubr.cool    1st version
+ */
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "fm24clxx.h"
+
+struct fm24clxx_device
+{
+    struct rt_device         parent;
+    struct rt_i2c_bus_device *bus;
+};
+
+/* RT-Thread device interface */
+
+static rt_err_t fm24clxx_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+static rt_err_t fm24clxx_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t fm24clxx_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t fm24clxx_control(rt_device_t dev, int cmd, void *args)
+{
+    return RT_EOK;
+}
+
+static rt_size_t fm24clxx_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    struct fm24clxx_device *fm24clxx;
+    const struct fm24clxx_config *cfg;
+    struct rt_i2c_msg msg[2];
+    rt_uint8_t mem_addr[2] = {0,};
+    rt_size_t ret = 0;
+    RT_ASSERT(dev != 0);
+
+    fm24clxx = (struct fm24clxx_device *) dev;
+
+    RT_ASSERT(fm24clxx->parent.user_data != 0);
+    cfg = (const struct fm24clxx_config *) fm24clxx->parent.user_data;
+
+    if(pos > cfg->size)
+    {
+         return 0;
+    }
+
+    if(pos + size > cfg->size)
+    {
+         size = cfg->size - pos;
+    }
+
+    msg[0].addr     = cfg->addr;
+    msg[0].flags    = cfg->flags | RT_I2C_WR;
+    mem_addr[0]     = (pos >> 8);
+    mem_addr[1]     = (rt_uint8_t) pos;
+    msg[0].buf      = (rt_uint8_t *) mem_addr;
+    msg[0].len      =  2;
+
+    msg[1].addr     = cfg->addr;
+    msg[1].flags    = cfg->flags | RT_I2C_RD;
+    msg[1].buf      = (rt_uint8_t *) buffer;
+    msg[1].len      = size;
+
+    ret = rt_i2c_transfer(fm24clxx->bus, msg, 2);
+    return (ret == 2) ? size : 0;
+}
+
+static rt_size_t fm24clxx_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    struct fm24clxx_device *fm24clxx;
+    const struct fm24clxx_config *cfg;
+    struct rt_i2c_msg msg[2];
+    rt_uint8_t mem_addr[2] = {0,};
+    rt_size_t ret = 0;
+    RT_ASSERT(dev != 0);
+
+    fm24clxx = (struct fm24clxx_device *) dev;
+
+    RT_ASSERT(fm24clxx->parent.user_data != 0);
+    cfg = (const struct fm24clxx_config *) fm24clxx->parent.user_data;
+
+    if(pos > cfg->size)
+    {
+         return 0;
+    }
+
+    if(pos + size > cfg->size)
+    {
+         size = cfg->size - pos;
+    }
+
+    msg[0].addr     = cfg->addr;
+    msg[0].flags    = cfg->flags | RT_I2C_WR;
+    mem_addr[0]     = (pos >> 8);
+    mem_addr[1]     = (rt_uint8_t) pos;
+    msg[0].buf      = (rt_uint8_t *) mem_addr;
+    msg[0].len      =  2;
+
+    msg[1].addr     = cfg->addr;
+    msg[1].flags    = cfg->flags | RT_I2C_WR | RT_I2C_NO_START;
+    msg[1].buf      = (rt_uint8_t *) buffer;
+    msg[1].len      = size;
+
+    ret = rt_i2c_transfer(fm24clxx->bus, msg, 2);
+    return (ret == 2) ? size : 0;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device fm24clxx_ops =
+{
+    fm24clxx_init,
+    fm24clxx_open,
+    fm24clxx_close,
+    fm24clxx_read,
+    fm24clxx_write,
+    fm24clxx_control
+};
+#endif
+
+rt_err_t fm24clxx_register(const char *fm_device_name, const char *i2c_bus, void *user_data)
+{
+    static struct fm24clxx_device fm24clxx_drv;
+    struct rt_i2c_bus_device *bus;
+
+    bus = rt_i2c_bus_device_find(i2c_bus);
+    if (bus == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    fm24clxx_drv.bus = bus;
+    fm24clxx_drv.parent.type      = RT_Device_Class_Block;
+#ifdef RT_USING_DEVICE_OPS
+    fm24clxx_drv.parent.ops       = &fm24clxx_ops;
+#else
+    fm24clxx_drv.parent.init      = fm24clxx_init;
+    fm24clxx_drv.parent.open      = fm24clxx_open;
+    fm24clxx_drv.parent.close     = fm24clxx_close;
+    fm24clxx_drv.parent.read      = fm24clxx_read;
+    fm24clxx_drv.parent.write     = fm24clxx_write;
+    fm24clxx_drv.parent.control   = fm24clxx_control;
+#endif
+
+    fm24clxx_drv.parent.user_data = user_data;
+
+    return rt_device_register(&fm24clxx_drv.parent, fm_device_name, RT_DEVICE_FLAG_RDWR);
+}

sysdrv/source/mcu/rt-thread/components/drivers/i2c/fm24clxx.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-07-14     aubr.cool    1st version
+ */
+
+#ifndef __FM24CLXX_H__
+#define __FM24CLXX_H__
+
+#include <rtthread.h>
+
+struct fm24clxx_config
+{
+    rt_uint32_t              size;
+    rt_uint16_t              addr;
+    rt_uint16_t              flags;
+};
+
+extern rt_err_t fm24clxx_register(const char *e2m_device_name,
+                                  const char *i2c_bus, void *user_data);
+
+#endif /*__FM24CLXX_H__*/

sysdrv/source/mcu/rt-thread/components/drivers/i2c/i2c-bit-ops.c

@@ -0,0 +1,443 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2012-04-25     weety         first version
+ */
+
+#include <rtdevice.h>
+
+#ifdef RT_I2C_BIT_DEBUG
+#define bit_dbg(fmt, ...)   rt_kprintf(fmt, ##__VA_ARGS__)
+#else
+#define bit_dbg(fmt, ...)
+#endif
+
+#define SET_SDA(ops, val)   ops->set_sda(ops->data, val)
+#define SET_SCL(ops, val)   ops->set_scl(ops->data, val)
+#define GET_SDA(ops)        ops->get_sda(ops->data)
+#define GET_SCL(ops)        ops->get_scl(ops->data)
+
+rt_inline void i2c_delay(struct rt_i2c_bit_ops *ops)
+{
+    ops->udelay((ops->delay_us + 1) >> 1);
+}
+
+rt_inline void i2c_delay2(struct rt_i2c_bit_ops *ops)
+{
+    ops->udelay(ops->delay_us);
+}
+
+#define SDA_L(ops)          SET_SDA(ops, 0)
+#define SDA_H(ops)          SET_SDA(ops, 1)
+#define SCL_L(ops)          SET_SCL(ops, 0)
+
+/**
+ * release scl line, and wait scl line to high.
+ */
+static rt_err_t SCL_H(struct rt_i2c_bit_ops *ops)
+{
+    rt_tick_t start;
+
+    SET_SCL(ops, 1);
+
+    if (!ops->get_scl)
+        goto done;
+
+    start = rt_tick_get();
+    while (!GET_SCL(ops))
+    {
+        if ((rt_tick_get() - start) > ops->timeout)
+            return -RT_ETIMEOUT;
+        rt_thread_delay((ops->timeout + 1) >> 1);
+    }
+#ifdef RT_I2C_BIT_DEBUG
+    if (rt_tick_get() != start)
+    {
+        bit_dbg("wait %ld tick for SCL line to go high\n",
+                rt_tick_get() - start);
+    }
+#endif
+
+done:
+    i2c_delay(ops);
+
+    return RT_EOK;
+}
+
+static void i2c_start(struct rt_i2c_bit_ops *ops)
+{
+#ifdef RT_I2C_BIT_DEBUG
+    if (ops->get_scl && !GET_SCL(ops))
+    {
+        bit_dbg("I2C bus error, SCL line low\n");
+    }
+    if (ops->get_sda && !GET_SDA(ops))
+    {
+        bit_dbg("I2C bus error, SDA line low\n");
+    }
+#endif
+    SDA_L(ops);
+    i2c_delay(ops);
+    SCL_L(ops);
+}
+
+static void i2c_restart(struct rt_i2c_bit_ops *ops)
+{
+    SDA_H(ops);
+    SCL_H(ops);
+    i2c_delay(ops);
+    SDA_L(ops);
+    i2c_delay(ops);
+    SCL_L(ops);
+}
+
+static void i2c_stop(struct rt_i2c_bit_ops *ops)
+{
+    SDA_L(ops);
+    i2c_delay(ops);
+    SCL_H(ops);
+    i2c_delay(ops);
+    SDA_H(ops);
+    i2c_delay2(ops);
+}
+
+rt_inline rt_bool_t i2c_waitack(struct rt_i2c_bit_ops *ops)
+{
+    rt_bool_t ack;
+
+    SDA_H(ops);
+    i2c_delay(ops);
+
+    if (SCL_H(ops) < 0)
+    {
+        bit_dbg("wait ack timeout\n");
+
+        return -RT_ETIMEOUT;
+    }
+
+    ack = !GET_SDA(ops);    /* ACK : SDA pin is pulled low */
+    bit_dbg("%s\n", ack ? "ACK" : "NACK");
+
+    SCL_L(ops);
+
+    return ack;
+}
+
+static rt_int32_t i2c_writeb(struct rt_i2c_bus_device *bus, rt_uint8_t data)
+{
+    rt_int32_t i;
+    rt_uint8_t bit;
+
+    struct rt_i2c_bit_ops *ops = bus->priv;
+
+    for (i = 7; i >= 0; i--)
+    {
+        SCL_L(ops);
+        bit = (data >> i) & 1;
+        SET_SDA(ops, bit);
+        i2c_delay(ops);
+        if (SCL_H(ops) < 0)
+        {
+            bit_dbg("i2c_writeb: 0x%02x, "
+                    "wait scl pin high timeout at bit %d\n",
+                    data, i);
+
+            return -RT_ETIMEOUT;
+        }
+    }
+    SCL_L(ops);
+    i2c_delay(ops);
+
+    return i2c_waitack(ops);
+}
+
+static rt_int32_t i2c_readb(struct rt_i2c_bus_device *bus)
+{
+    rt_uint8_t i;
+    rt_uint8_t data = 0;
+    struct rt_i2c_bit_ops *ops = bus->priv;
+
+    SDA_H(ops);
+    i2c_delay(ops);
+    for (i = 0; i < 8; i++)
+    {
+        data <<= 1;
+
+        if (SCL_H(ops) < 0)
+        {
+            bit_dbg("i2c_readb: wait scl pin high "
+                    "timeout at bit %d\n", 7 - i);
+
+            return -RT_ETIMEOUT;
+        }
+
+        if (GET_SDA(ops))
+            data |= 1;
+        SCL_L(ops);
+        i2c_delay2(ops);
+    }
+
+    return data;
+}
+
+static rt_size_t i2c_send_bytes(struct rt_i2c_bus_device *bus,
+                                struct rt_i2c_msg        *msg)
+{
+    rt_int32_t ret;
+    rt_size_t bytes = 0;
+    const rt_uint8_t *ptr = msg->buf;
+    rt_int32_t count = msg->len;
+    rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+
+    while (count > 0)
+    {
+        ret = i2c_writeb(bus, *ptr);
+
+        if ((ret > 0) || (ignore_nack && (ret == 0)))
+        {
+            count --;
+            ptr ++;
+            bytes ++;
+        }
+        else if (ret == 0)
+        {
+            i2c_dbg("send bytes: NACK.\n");
+
+            return 0;
+        }
+        else
+        {
+            i2c_dbg("send bytes: error %d\n", ret);
+
+            return ret;
+        }
+    }
+
+    return bytes;
+}
+
+static rt_err_t i2c_send_ack_or_nack(struct rt_i2c_bus_device *bus, int ack)
+{
+    struct rt_i2c_bit_ops *ops = bus->priv;
+
+    if (ack)
+        SET_SDA(ops, 0);
+    i2c_delay(ops);
+    if (SCL_H(ops) < 0)
+    {
+        bit_dbg("ACK or NACK timeout\n");
+
+        return -RT_ETIMEOUT;
+    }
+    SCL_L(ops);
+
+    return RT_EOK;
+}
+
+static rt_size_t i2c_recv_bytes(struct rt_i2c_bus_device *bus,
+                                struct rt_i2c_msg        *msg)
+{
+    rt_int32_t val;
+    rt_int32_t bytes = 0;   /* actual bytes */
+    rt_uint8_t *ptr = msg->buf;
+    rt_int32_t count = msg->len;
+    const rt_uint32_t flags = msg->flags;
+
+    while (count > 0)
+    {
+        val = i2c_readb(bus);
+        if (val >= 0)
+        {
+            *ptr = val;
+            bytes ++;
+        }
+        else
+        {
+            break;
+        }
+
+        ptr ++;
+        count --;
+
+        bit_dbg("recieve bytes: 0x%02x, %s\n",
+                val, (flags & RT_I2C_NO_READ_ACK) ?
+                "(No ACK/NACK)" : (count ? "ACK" : "NACK"));
+
+        if (!(flags & RT_I2C_NO_READ_ACK))
+        {
+            val = i2c_send_ack_or_nack(bus, count);
+            if (val < 0)
+                return val;
+        }
+    }
+
+    return bytes;
+}
+
+static rt_int32_t i2c_send_address(struct rt_i2c_bus_device *bus,
+                                   rt_uint8_t                addr,
+                                   rt_int32_t                retries)
+{
+    struct rt_i2c_bit_ops *ops = bus->priv;
+    rt_int32_t i;
+    rt_err_t ret = 0;
+
+    for (i = 0; i <= retries; i++)
+    {
+        ret = i2c_writeb(bus, addr);
+        if (ret == 1 || i == retries)
+            break;
+        bit_dbg("send stop condition\n");
+        i2c_stop(ops);
+        i2c_delay2(ops);
+        bit_dbg("send start condition\n");
+        i2c_start(ops);
+    }
+
+    return ret;
+}
+
+static rt_err_t i2c_bit_send_address(struct rt_i2c_bus_device *bus,
+                                     struct rt_i2c_msg        *msg)
+{
+    rt_uint16_t flags = msg->flags;
+    rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+    struct rt_i2c_bit_ops *ops = bus->priv;
+
+    rt_uint8_t addr1, addr2;
+    rt_int32_t retries;
+    rt_err_t ret;
+
+    retries = ignore_nack ? 0 : bus->retries;
+
+    if (flags & RT_I2C_ADDR_10BIT)
+    {
+        addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
+        addr2 = msg->addr & 0xff;
+
+        bit_dbg("addr1: %d, addr2: %d\n", addr1, addr2);
+
+        ret = i2c_send_address(bus, addr1, retries);
+        if ((ret != 1) && !ignore_nack)
+        {
+            bit_dbg("NACK: sending first addr\n");
+
+            return -RT_EIO;
+        }
+
+        ret = i2c_writeb(bus, addr2);
+        if ((ret != 1) && !ignore_nack)
+        {
+            bit_dbg("NACK: sending second addr\n");
+
+            return -RT_EIO;
+        }
+        if (flags & RT_I2C_RD)
+        {
+            bit_dbg("send repeated start condition\n");
+            i2c_restart(ops);
+            addr1 |= 0x01;
+            ret = i2c_send_address(bus, addr1, retries);
+            if ((ret != 1) && !ignore_nack)
+            {
+                bit_dbg("NACK: sending repeated addr\n");
+
+                return -RT_EIO;
+            }
+        }
+    }
+    else
+    {
+        /* 7-bit addr */
+        addr1 = msg->addr << 1;
+        if (flags & RT_I2C_RD)
+            addr1 |= 1;
+        ret = i2c_send_address(bus, addr1, retries);
+        if ((ret != 1) && !ignore_nack)
+            return -RT_EIO;
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t i2c_bit_xfer(struct rt_i2c_bus_device *bus,
+                              struct rt_i2c_msg         msgs[],
+                              rt_uint32_t               num)
+{
+    struct rt_i2c_msg *msg;
+    struct rt_i2c_bit_ops *ops = bus->priv;
+    rt_int32_t i, ret;
+    rt_uint16_t ignore_nack;
+
+    bit_dbg("send start condition\n");
+    i2c_start(ops);
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+        if (!(msg->flags & RT_I2C_NO_START))
+        {
+            if (i)
+            {
+                i2c_restart(ops);
+            }
+            ret = i2c_bit_send_address(bus, msg);
+            if ((ret != RT_EOK) && !ignore_nack)
+            {
+                bit_dbg("receive NACK from device addr 0x%02x msg %d\n",
+                        msgs[i].addr, i);
+                goto out;
+            }
+        }
+        if (msg->flags & RT_I2C_RD)
+        {
+            ret = i2c_recv_bytes(bus, msg);
+            if (ret >= 1)
+                bit_dbg("read %d byte%s\n", ret, ret == 1 ? "" : "s");
+            if (ret < msg->len)
+            {
+                if (ret >= 0)
+                    ret = -RT_EIO;
+                goto out;
+            }
+        }
+        else
+        {
+            ret = i2c_send_bytes(bus, msg);
+            if (ret >= 1)
+                bit_dbg("write %d byte%s\n", ret, ret == 1 ? "" : "s");
+            if (ret < msg->len)
+            {
+                if (ret >= 0)
+                    ret = -RT_ERROR;
+                goto out;
+            }
+        }
+    }
+    ret = i;
+
+out:
+    bit_dbg("send stop condition\n");
+    i2c_stop(ops);
+
+    return ret;
+}
+
+static const struct rt_i2c_bus_device_ops i2c_bit_bus_ops =
+{
+    i2c_bit_xfer,
+    RT_NULL,
+    RT_NULL
+};
+
+rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
+                            const char               *bus_name)
+{
+    bus->ops = &i2c_bit_bus_ops;
+
+    return rt_i2c_bus_device_register(bus, bus_name);
+}

sysdrv/source/mcu/rt-thread/components/drivers/i2c/i2c_core.c

@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2012-04-25     weety         first version
+ */
+
+#include <rtdevice.h>
+
+rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus,
+                                    const char               *bus_name)
+{
+    rt_err_t res = RT_EOK;
+
+    rt_mutex_init(&bus->lock, "i2c_bus_lock", RT_IPC_FLAG_FIFO);
+
+    if (bus->timeout == 0) bus->timeout = RT_TICK_PER_SECOND;
+
+    res = rt_i2c_bus_device_device_init(bus, bus_name);
+
+    i2c_dbg("I2C bus [%s] registered\n", bus_name);
+
+    return res;
+}
+
+struct rt_i2c_bus_device *rt_i2c_bus_device_find(const char *bus_name)
+{
+    struct rt_i2c_bus_device *bus;
+    rt_device_t dev = rt_device_find(bus_name);
+    if (dev == RT_NULL || dev->type != RT_Device_Class_I2CBUS)
+    {
+        i2c_dbg("I2C bus %s not exist\n", bus_name);
+
+        return RT_NULL;
+    }
+
+    bus = (struct rt_i2c_bus_device *)dev->user_data;
+
+    return bus;
+}
+
+rt_size_t rt_i2c_transfer(struct rt_i2c_bus_device *bus,
+                          struct rt_i2c_msg         msgs[],
+                          rt_uint32_t               num)
+{
+    rt_size_t ret;
+
+    if (bus->ops->master_xfer)
+    {
+#ifdef RT_I2C_DEBUG
+        for (ret = 0; ret < num; ret++)
+        {
+            i2c_dbg("msgs[%d] %c, addr=0x%02x, len=%d\n", ret,
+                    (msgs[ret].flags & RT_I2C_RD) ? 'R' : 'W',
+                    msgs[ret].addr, msgs[ret].len);
+        }
+#endif
+
+        rt_mutex_take(&bus->lock, RT_WAITING_FOREVER);
+        ret = bus->ops->master_xfer(bus, msgs, num);
+        rt_mutex_release(&bus->lock);
+
+        return ret;
+    }
+    else
+    {
+        i2c_dbg("I2C bus operation not supported\n");
+
+        return 0;
+    }
+}
+
+rt_size_t rt_i2c_master_send(struct rt_i2c_bus_device *bus,
+                             rt_uint16_t               addr,
+                             rt_uint16_t               flags,
+                             const rt_uint8_t         *buf,
+                             rt_uint32_t               count)
+{
+    rt_err_t ret;
+    struct rt_i2c_msg msg;
+
+    msg.addr  = addr;
+    msg.flags = flags & RT_I2C_ADDR_10BIT;
+    msg.len   = count;
+    msg.buf   = (rt_uint8_t *)buf;
+
+    ret = rt_i2c_transfer(bus, &msg, 1);
+
+    return (ret > 0) ? count : ret;
+}
+
+rt_size_t rt_i2c_master_recv(struct rt_i2c_bus_device *bus,
+                             rt_uint16_t               addr,
+                             rt_uint16_t               flags,
+                             rt_uint8_t               *buf,
+                             rt_uint32_t               count)
+{
+    rt_err_t ret;
+    struct rt_i2c_msg msg;
+    RT_ASSERT(bus != RT_NULL);
+
+    msg.addr   = addr;
+    msg.flags  = flags & RT_I2C_ADDR_10BIT;
+    msg.flags |= RT_I2C_RD;
+    msg.len    = count;
+    msg.buf    = buf;
+
+    ret = rt_i2c_transfer(bus, &msg, 1);
+
+    return (ret > 0) ? count : ret;
+}
+
+int rt_i2c_core_init(void)
+{
+    return 0;
+}
+INIT_COMPONENT_EXPORT(rt_i2c_core_init);

sysdrv/source/mcu/rt-thread/components/drivers/i2c/i2c_dev.c

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2012-04-25     weety         first version
+ * 2014-08-03     bernard       fix some compiling warning
+ */
+
+#include <rtdevice.h>
+
+static rt_size_t i2c_bus_device_read(rt_device_t dev,
+                                     rt_off_t    pos,
+                                     void       *buffer,
+                                     rt_size_t   count)
+{
+    rt_uint16_t addr;
+    rt_uint16_t flags;
+    struct rt_i2c_bus_device *bus = (struct rt_i2c_bus_device *)dev->user_data;
+
+    RT_ASSERT(bus != RT_NULL);
+    RT_ASSERT(buffer != RT_NULL);
+
+    i2c_dbg("I2C bus dev [%s] reading %u bytes.\n", dev->parent.name, count);
+
+    addr = pos & 0xffff;
+    flags = (pos >> 16) & 0xffff;
+
+    return rt_i2c_master_recv(bus, addr, flags, buffer, count);
+}
+
+static rt_size_t i2c_bus_device_write(rt_device_t dev,
+                                      rt_off_t    pos,
+                                      const void *buffer,
+                                      rt_size_t   count)
+{
+    rt_uint16_t addr;
+    rt_uint16_t flags;
+    struct rt_i2c_bus_device *bus = (struct rt_i2c_bus_device *)dev->user_data;
+
+    RT_ASSERT(bus != RT_NULL);
+    RT_ASSERT(buffer != RT_NULL);
+
+    i2c_dbg("I2C bus dev [%s] writing %u bytes.\n", dev->parent.name, count);
+
+    addr = pos & 0xffff;
+    flags = (pos >> 16) & 0xffff;
+
+    return rt_i2c_master_send(bus, addr, flags, buffer, count);
+}
+
+static rt_err_t i2c_bus_device_control(rt_device_t dev,
+                                       int         cmd,
+                                       void       *args)
+{
+    rt_err_t ret;
+    struct rt_i2c_priv_data *priv_data;
+    struct rt_i2c_bus_device *bus = (struct rt_i2c_bus_device *)dev->user_data;
+
+    RT_ASSERT(bus != RT_NULL);
+
+    switch (cmd)
+    {
+    /* set 10-bit addr mode */
+    case RT_I2C_DEV_CTRL_10BIT:
+        bus->flags |= RT_I2C_ADDR_10BIT;
+        break;
+    case RT_I2C_DEV_CTRL_ADDR:
+        bus->addr = *(rt_uint16_t *)args;
+        break;
+    case RT_I2C_DEV_CTRL_TIMEOUT:
+        bus->timeout = *(rt_uint32_t *)args;
+        break;
+    case RT_I2C_DEV_CTRL_RW:
+        priv_data = (struct rt_i2c_priv_data *)args;
+        ret = rt_i2c_transfer(bus, priv_data->msgs, priv_data->number);
+        if (ret < 0)
+        {
+            return -RT_EIO;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return RT_EOK;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops i2c_ops = 
+{
+    RT_NULL, 
+    RT_NULL,
+    RT_NULL,
+    i2c_bus_device_read,
+    i2c_bus_device_write,
+    i2c_bus_device_control
+};
+#endif
+
+rt_err_t rt_i2c_bus_device_device_init(struct rt_i2c_bus_device *bus,
+                                       const char               *name)
+{
+    struct rt_device *device;
+    RT_ASSERT(bus != RT_NULL);
+
+    device = &bus->parent;
+
+    device->user_data = bus;
+
+    /* set device type */
+    device->type    = RT_Device_Class_I2CBUS;
+    /* initialize device interface */
+#ifdef RT_USING_DEVICE_OPS
+    device->ops     = &i2c_ops;
+#else
+    device->init    = RT_NULL;
+    device->open    = RT_NULL;
+    device->close   = RT_NULL;
+    device->read    = i2c_bus_device_read;
+    device->write   = i2c_bus_device_write;
+    device->control = i2c_bus_device_control;
+#endif
+
+    /* register to device manager */
+    rt_device_register(device, name, RT_DEVICE_FLAG_RDWR);
+
+    return RT_EOK;
+}