mirror of
https://github.com/LuckfoxTECH/luckfox-pico.git
synced 2026-01-19 17:59:18 +01:00
project:build.sh: Added fastboot support; custom modifications to U-Boot and kernel implemented using patches.
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
This commit is contained in:
luckfox-eng29
@@ -9,7 +9,6 @@
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#include <linux/mfd/syscon.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/rtc.h>
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@@ -62,6 +61,7 @@
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/* RTC_CTRL_REG bitfields */
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#define RTC_CTRL_REG_START_RTC BIT(0)
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#define RTC_TIMEOUT (3000 * 1000)
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/* RK630 has a shadowed register for saving a "frozen" RTC time.
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* When user setting "GET_TIME" to 1, the time will save in this shadowed
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@@ -86,6 +86,7 @@
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#define RTC_VREF_INIT 0x40
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#define CLK_32K_ENABLE BIT(5)
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#define D2A_POR_REG_SEL1 BIT(4)
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#define D2A_POR_REG_SEL0 BIT(1)
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@@ -100,7 +101,7 @@
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#define CLK32K_TEST_START BIT(0)
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#define CLK32K_TEST_STATUS BIT(1)
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#define CLK32K_TEST_DONE BIT(2)
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#define CLK32K_TEST_LEN 2
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#define CLK32K_TEST_LEN 1
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#define CLK32K_COMP_DIR_ADD BIT(7)
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#define CLK32K_COMP_EN BIT(2)
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@@ -123,6 +124,8 @@ struct rockchip_rtc {
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int irq;
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unsigned int flag;
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unsigned int mode;
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struct delayed_work trim_work;
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bool suspend_bypass;
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};
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static unsigned int rockchip_rtc_write(struct regmap *map,
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@@ -221,15 +224,14 @@ static int rockchip_rtc_set_time(struct device *dev, struct rtc_time *tm)
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dev_err(dev, "Failed to update RTC control: %d\n", ret);
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return ret;
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}
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ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
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while (status & RTC_CTRL_REG_START_RTC) {
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udelay(1);
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ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
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if (ret) {
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dev_err(dev, "Failed to read RTC_STATUS1: %d\n", ret);
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return ret;
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}
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}
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ret = regmap_read_poll_timeout(rtc->regmap, RTC_STATUS1, status,
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!(status & RTC_CTRL_REG_START_RTC),
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0, RTC_TIMEOUT);
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if (ret)
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dev_err(dev,
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"%s:timeout Update RTC_STATUS1 : %d\n",
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__func__, ret);
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ret = regmap_bulk_write(rtc->regmap, RTC_SET_SECONDS,
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rtc_data, NUM_TIME_REGS);
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@@ -248,15 +250,15 @@ static int rockchip_rtc_set_time(struct device *dev, struct rtc_time *tm)
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dev_err(dev, "Failed to update RTC control: %d\n", ret);
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return ret;
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}
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ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
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while (!(status & RTC_CTRL_REG_START_RTC)) {
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udelay(1);
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ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
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if (ret) {
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dev_err(dev, "Failed to read RTC_STATUS1: %d\n", ret);
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return ret;
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}
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}
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ret = regmap_read_poll_timeout(rtc->regmap, RTC_STATUS1, status,
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(status & RTC_CTRL_REG_START_RTC),
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0, RTC_TIMEOUT);
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if (ret)
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dev_err(dev,
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"%s:timeout Update RTC_STATUS1 : %d\n",
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__func__, ret);
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return 0;
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}
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@@ -443,10 +445,9 @@ static const struct rtc_class_ops rockchip_rtc_ops = {
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* in last hour in last day every month,
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* and support add time and sub time by the MSB bit.
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*/
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static int rockchip_rtc_compensation(struct device *dev)
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static void rockchip_rtc_compensation_delay_work(struct work_struct *work)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
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struct rockchip_rtc *rtc = container_of(work, struct rockchip_rtc, trim_work.work);
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u64 camp;
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u32 count[4], counts, g_ref, tcamp;
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int ret, done = 0, trim_dir, c_hour,
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@@ -455,44 +456,39 @@ static int rockchip_rtc_compensation(struct device *dev)
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ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CLK32K_TEST,
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CLK32K_TEST_EN, CLK32K_TEST_EN);
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if (ret) {
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dev_err(dev,
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"%s:Failed to update RTC CLK32K TEST: %d\n",
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__func__, ret);
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return ret;
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pr_err("%s:Failed to update RTC CLK32K TEST: %d\n",
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__func__, ret);
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return;
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}
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ret = rockchip_rtc_write(rtc->regmap, RTC_TEST_LEN,
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CLK32K_TEST_LEN);
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if (ret) {
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dev_err(dev,
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"%s:Failed to update RTC CLK32K TEST LEN: %d\n",
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__func__, ret);
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return ret;
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pr_err("%s:Failed to update RTC CLK32K TEST LEN: %d\n",
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__func__, ret);
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return;
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}
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ret = rockchip_rtc_update_bits(rtc->regmap, RTC_TEST_ST,
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CLK32K_TEST_START,
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CLK32K_TEST_START);
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if (ret) {
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dev_err(dev,
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"%s:Failed to update RTC CLK32K TEST STATUS : %d\n",
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__func__, ret);
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return ret;
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pr_err("%s:Failed to update RTC CLK32K TEST STATUS : %d\n",
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__func__, ret);
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return;
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}
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ret = regmap_read_poll_timeout(rtc->regmap, RTC_TEST_ST, done,
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(done & CLK32K_TEST_DONE), 0, 1000);
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(done & CLK32K_TEST_DONE), 20000, RTC_TIMEOUT);
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if (ret)
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dev_err(dev,
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"%s:timeout waiting for RTC TEST STATUS : %d\n",
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__func__, ret);
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pr_err("%s:timeout waiting for RTC TEST STATUS : %d\n",
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__func__, ret);
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ret = regmap_bulk_read(rtc->regmap,
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RTC_CNT_0,
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count, 4);
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if (ret) {
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dev_err(dev, "Failed to read RTC count REG: %d\n", ret);
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return ret;
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pr_err("Failed to read RTC count REG: %d\n", ret);
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return;
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}
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counts = count[0] | (count[1] << 8) |
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@@ -514,7 +510,7 @@ static int rockchip_rtc_compensation(struct device *dev)
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c_mon = DIV_ROUND_CLOSEST(30 * 24 * tcamp, 32768);
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if (c_hour > 1)
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rockchip_rtc_write(rtc->regmap, RTC_COMP_H, (c_hour - 1) | trim_dir);
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rockchip_rtc_write(rtc->regmap, RTC_COMP_H, bin2bcd((c_hour - 1)) | trim_dir);
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else
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rockchip_rtc_write(rtc->regmap, RTC_COMP_H, CLK32K_NO_COMP);
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@@ -528,7 +524,7 @@ static int rockchip_rtc_compensation(struct device *dev)
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if (c_det_day > 1)
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rockchip_rtc_write(rtc->regmap, RTC_COMP_D,
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(c_det_day - 1) | trim_dir);
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bin2bcd((c_det_day - 1)) | trim_dir);
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else
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rockchip_rtc_write(rtc->regmap, RTC_COMP_D, CLK32K_NO_COMP);
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@@ -542,24 +538,48 @@ static int rockchip_rtc_compensation(struct device *dev)
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if (c_det_mon)
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rockchip_rtc_write(rtc->regmap, RTC_COMP_M,
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(c_det_mon - 1) | trim_dir);
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bin2bcd((c_det_mon - 1)) | trim_dir);
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else
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rockchip_rtc_write(rtc->regmap, RTC_COMP_M, CLK32K_NO_COMP);
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ret = regmap_read(rtc->regmap, RTC_CTRL, &done);
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if (ret) {
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dev_err(dev, "Failed to read RTC_CTRL: %d\n", ret);
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return ret;
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pr_err("Failed to read RTC_CTRL: %d\n", ret);
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return;
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}
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ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
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CLK32K_COMP_EN, CLK32K_COMP_EN);
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if (ret) {
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dev_err(dev,
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"%s:Failed to update RTC CTRL : %d\n", __func__, ret);
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return ret;
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pr_err("%s:Failed to update RTC CTRL : %d\n", __func__, ret);
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return;
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}
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return 0;
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return;
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}
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static bool rockchip_rtc_is_trimed(struct rockchip_rtc *rtc)
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{
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int ret, comp_done;
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ret = regmap_read(rtc->regmap, RTC_CTRL, &comp_done);
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if (ret) {
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pr_err("%s: Failed to read RTC_CTRL: %d\n", __func__, ret);
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return false;
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}
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return (comp_done & CLK32K_COMP_EN) == CLK32K_COMP_EN;
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}
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static void rockchip_rtc_trim_start(struct rockchip_rtc *rtc)
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{
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if (!rockchip_rtc_is_trimed(rtc))
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queue_delayed_work(system_long_wq, &rtc->trim_work,
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msecs_to_jiffies(5000));
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}
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static void __maybe_unused rockchip_rtc_trim_close(struct rockchip_rtc *rtc)
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{
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if (!rockchip_rtc_is_trimed(rtc))
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cancel_delayed_work_sync(&rtc->trim_work);
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}
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/* Enable the alarm if it should be enabled (in case it was disabled to
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@@ -572,9 +592,14 @@ static int rockchip_rtc_suspend(struct device *dev)
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struct platform_device *pdev = to_platform_device(dev);
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struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
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if (rtc->suspend_bypass)
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return 0;
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if (device_may_wakeup(dev))
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enable_irq_wake(rtc->irq);
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rockchip_rtc_trim_close(rtc);
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if (rtc->grf) {
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switch (rtc->mode) {
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case ROCKCHIP_RV1106_RTC:
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@@ -599,6 +624,9 @@ static int rockchip_rtc_resume(struct device *dev)
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struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
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int ret;
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if (rtc->suspend_bypass)
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return 0;
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if (device_may_wakeup(dev))
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disable_irq_wake(rtc->irq);
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@@ -617,6 +645,7 @@ static int rockchip_rtc_resume(struct device *dev)
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dev_err(dev, "Cannot enable clock.\n");
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return ret;
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}
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rockchip_rtc_trim_start(rtc);
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return 0;
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}
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@@ -666,7 +695,7 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
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return dev_err_probe(dev, PTR_ERR(rtc->regmap),
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"no regmap available\n");
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rtc->mode = (unsigned int)of_device_get_match_data(&pdev->dev);
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rtc->mode = (uintptr_t)device_get_match_data(dev);
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rtc->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
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if (IS_ERR(rtc->grf)) {
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dev_warn(dev, "Missing rockchip,grf property\n");
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@@ -696,8 +725,10 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
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"Failed to add clk disable action.");
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ret = rockchip_rtc_update_bits(rtc->regmap, RTC_VPTAT_TRIM,
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D2A_POR_REG_SEL1,
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D2A_POR_REG_SEL1);
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D2A_POR_REG_SEL1 |
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CLK_32K_ENABLE,
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D2A_POR_REG_SEL1 |
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CLK_32K_ENABLE);
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if (ret)
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return dev_err_probe(&pdev->dev, ret,
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"Failed to write RTC_VPTAT_TRIM\n");
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@@ -722,8 +753,6 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
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return dev_err_probe(&pdev->dev, ret,
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"Failed to update RTC_ANALOG_EN\n");
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rockchip_rtc_compensation(&pdev->dev);
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/* start rtc running by default, and use shadowed timer. */
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ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
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RTC_CTRL_REG_START_RTC |
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@@ -769,6 +798,13 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
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"Failed to request alarm IRQ %d\n",
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rtc->irq);
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/* If rtc 32k used as time for deep sleep, the rtc suspend func bypass do nothing. */
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rtc->suspend_bypass = device_property_read_bool(&pdev->dev,
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"rockchip,rtc-suspend-bypass");
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INIT_DELAYED_WORK(&rtc->trim_work, rockchip_rtc_compensation_delay_work);
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rockchip_rtc_trim_start(rtc);
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return rtc_register_device(rtc->rtc);
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}
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