mirror of
https://github.com/LuckfoxTECH/luckfox-pico.git
synced 2026-01-18 03:28:19 +01:00
project:build.sh: Added fastboot support; custom modifications to U-Boot and kernel implemented using patches.
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
This commit is contained in:
luckfox-eng29
@@ -1,408 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include "rv1106-amp.dtsi"
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/ {
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff4c0000 console=ttyFIQ0 root=/dev/mmcblk1p7 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0";
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};
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acodec_sound: acodec-sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "rv-acodec";
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simple-audio-card,format = "i2s";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,cpu {
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sound-dai = <&i2s0_8ch>;
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};
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simple-audio-card,codec {
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sound-dai = <&acodec>;
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};
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};
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vcc_1v8: vcc-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vcc_3v3: vcc-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdd_arm: vdd-arm {
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compatible = "regulator-fixed";
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regulator-name = "vdd_arm";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-always-on;
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regulator-boot-on;
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};
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leds: leds {
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compatible = "gpio-leds";
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work_led: work{
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gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "activity";
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default-state = "on";
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};
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};
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// DHT11
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dht11_sensor {
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compatible = "dht11";
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pinctrl-names = "default";
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pinctrl-0 = <&gpio1_pc7>;
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dht11@1 {
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gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
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label = "dht11";
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linux,default-trigger = "humidity";
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};
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};
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};
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/***************************** AUDIO ********************************/
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&i2s0_8ch {
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#sound-dai-cells = <0>;
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status = "okay";
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};
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&acodec {
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#sound-dai-cells = <0>;
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pa-ctl-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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/***************************** CPU ********************************/
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&cpu0 {
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cpu-supply = <&vdd_arm>;
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};
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/***************************** ADC ********************************/
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&saradc {
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status = "okay";
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vref-supply = <&vcc_1v8>;
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};
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&tsadc {
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status = "okay";
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};
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/***************************** CSI ********************************/
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&csi2_dphy_hw {
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status = "okay";
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};
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&csi2_dphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy_input0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&sc3336_out>;
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data-lanes = <1 2>;
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};
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csi_dphy_input1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&sc4336_out>;
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data-lanes = <1 2>;
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};
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csi_dphy_input2: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&sc530ai_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_csi2_input>;
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};
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};
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};
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};
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&i2c4 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4m2_xfer>;
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sc3336: sc3336@30 {
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compatible = "smartsens,sc3336";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru MCLK_REF_MIPI0>;
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clock-names = "xvclk";
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pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_refclk_out0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "CMK-OT2119-PC1";
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rockchip,camera-module-lens-name = "30IRC-F16";
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port {
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sc3336_out: endpoint {
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remote-endpoint = <&csi_dphy_input0>;
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data-lanes = <1 2>;
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};
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};
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};
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sc4336: sc4336@30 {
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compatible = "smartsens,sc4336";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru MCLK_REF_MIPI0>;
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clock-names = "xvclk";
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pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_refclk_out0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "OT01";
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rockchip,camera-module-lens-name = "40IRC_F16";
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port {
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sc4336_out: endpoint {
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remote-endpoint = <&csi_dphy_input1>;
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data-lanes = <1 2>;
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};
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};
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};
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sc530ai: sc530ai@30 {
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compatible = "smartsens,sc530ai";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru MCLK_REF_MIPI0>;
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clock-names = "xvclk";
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pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_refclk_out0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "CMK-OT2115-PC1";
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rockchip,camera-module-lens-name = "30IRC-F16";
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port {
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sc530ai_out: endpoint {
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remote-endpoint = <&csi_dphy_input2>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&mipi0_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csi_dphy_output>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in>;
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};
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};
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};
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};
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&rkcif {
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status = "okay";
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};
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&rkcif_mipi_lvds {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_pins>;
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port {
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/* MIPI CSI-2 endpoint */
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cif_mipi_in: endpoint {
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remote-endpoint = <&mipi_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds_sditf {
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status = "okay";
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port {
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/* MIPI CSI-2 endpoint */
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mipi_lvds_sditf: endpoint {
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remote-endpoint = <&isp_in>;
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};
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};
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};
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&rkisp {
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status = "okay";
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};
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&rkisp_vir0 {
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status = "okay";
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port@0 {
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isp_in: endpoint {
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remote-endpoint = <&mipi_lvds_sditf>;
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};
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};
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};
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/*****************************PINCTRL********************************/
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// SPI
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&spi0 {
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pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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spidev@0 {
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compatible = "rockchip,spidev";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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fbtft@0{
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compatible = "sitronix,st7789v";
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reg = <0>;
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spi-max-frequency = <20000000>;
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fps = <30>;
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buswidth = <8>;
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debug = <0x7>;
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led-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;//BL
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dc = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; //DC
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reset = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; //RES
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};
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};
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// I2C
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&i2c0 {
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pinctrl-0 = <&i2c0m2_xfer>;
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};
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&i2c1 {
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pinctrl-0 = <&i2c1m1_xfer>;
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};
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&i2c3 {
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pinctrl-0 = <&i2c3m1_xfer &i2c3m0_xfer>;
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};
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// &i2c4 {
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// pinctrl-0 = <&i2c4m0_xfer>;
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// };
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// UART
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&uart0 {
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pinctrl-0 = <&uart0m0_xfer &uart0m1_xfer>;
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};
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&uart1 {
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pinctrl-0 = <&uart1m1_xfer>;
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};
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&uart3 {
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pinctrl-0 = <&uart3m1_xfer>;
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};
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&uart4 {
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pinctrl-0 = <&uart4m1_xfer>;
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};
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&uart5 {
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pinctrl-0 = <&uart5m0_xfer>;
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};
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// PWM
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&pwm0 {
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pinctrl-0 = <&pwm0m1_pins>;
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};
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&pwm2 {
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pinctrl-0 = <&pwm2m2_pins>;
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};
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&pwm3 {
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pinctrl-0 = <&pwm3m2_pins>;
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};
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&pwm4 {
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pinctrl-0 = <&pwm4m2_pins>;
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};
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&pwm5 {
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pinctrl-0 = <&pwm5m2_pins>;
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};
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&pwm6 {
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pinctrl-0 = <&pwm6m1_pins &pwm6m2_pins>;
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};
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&pwm8 {
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pinctrl-0 = <&pwm8m1_pins>;
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};
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&pwm9 {
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pinctrl-0 = <&pwm9m1_pins>;
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};
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&pwm10 {
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pinctrl-0 = <&pwm10m2_pins>;
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};
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&pwm11 {
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pinctrl-0 = <&pwm11m1_pins>;
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};
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&pinctrl {
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spi0 {
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spi0m0_clk: spi0m0-clk {
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rockchip,pins = <1 RK_PC1 4 &pcfg_pull_none>;
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};
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spi0m0_mosi: spi0m0-mosi {
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rockchip,pins = <1 RK_PC2 6 &pcfg_pull_none>;
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};
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spi0m0_miso: spi0m0-miso {
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rockchip,pins = <1 RK_PC3 6 &pcfg_pull_none>;
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};
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spi0m0_cs0: spi0m0-cs0 {
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rockchip,pins = <1 RK_PC0 4 &pcfg_pull_none>;
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};
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};
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gpio1-pc7 {
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gpio1_pc7:gpio1-pc7 {
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rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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Reference in New Issue
Block a user